Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain

Patent metadata

Field	Value
Publication number	US-9716170-B1
Application number	US-201615282398-A
Country	US
Kind code	B1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.

First claim

What is claimed is:

1. A method of forming gate and source or drain features of a vertical field effect transistor (FET), the method comprising:
forming a fin in a substrate;
forming a source or a drain region in the substrate;
forming a trench in the source or the drain region;
forming a dielectric region in the trench;
forming a gate along vertical sidewalls of the fin such that a space between the gate and the source or the drain region comprises at least a portion of the dielectric region; and
forming a bottom spacer over an upper surface of the dielectric region such that the space between the gate and the source or the drain region further comprises at least a portion of the bottom spacer.

2. The method of claim 1 , wherein the fin comprises an upper fin region and a lower base region.

3. The method of claim 2 , wherein the lower base region includes an upper surface and a base width dimension.

4. The method of claim 3 , wherein the upper fin region includes an upper fin width dimension.

5. The method of claim 4 , wherein the base width dimension is greater than the upper fin width dimension.

6. The method of claim 5 , wherein the dielectric region comprises a low-k material and the bottom spacer comprises a high-k material.

7. The method of claim 1 , wherein forming the trench comprises:
forming the fin to include an upper fin region and a lower base region, wherein the lower base region includes an upper surface, the lower base region includes a base width dimension, the upper fin region includes an upper fin width dimension, the base width dimension is greater than the upper fin width dimension, and at least a portion of the trench comprises an upper surface of the lower base region.

8. The method of claim 7 , wherein the dielectric region comprises a low-k material and the spacer comprises a high-k material.

9. The method of claim 7 , wherein at least a portion of the source or the drain region is formed from the lower base region.

10. The method of claim 9 , wherein the upper surface of the lower base region is formed at an angle with respect to a major surface of the substrate.

11. The method of claim 10 , wherein the angle comprises greater than zero degrees and less than ninety degrees.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Xie Ruilong
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H01L29/41741

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title