Vertical transistor with air-gap spacer

Patent metadata

Field	Value
Publication number	US-9691850-B2
Application number	US-201615163059-A
Country	US
Kind code	B2
Filing date	May 24, 2016
Priority date	Nov 21, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

First claim

What is claimed as new is:

1. A vertical transistor comprising:
a fin or nanowire disposed over a semiconductor substrate;
a gate electrode formed over sidewalls of the fin or nanowire;
a bottom source/drain contact adjacent to the gate electrode;
a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap; and
a bottom source/drain region located between the fin or the nanowire and a top semiconductor layer of the semiconductor substrate, the bottom source/drain region is laterally separated from the bottom source/drain contact by a bottom spacer.

2. The vertical transistor of claim 1 , wherein a topmost surface of the bottom spacer is coplanar with a topmost surface of the bottom source/drain region.

3. The vertical transistor of claim 1 , wherein the vertical air-gap present within the dielectric spacer is disposed above a portion of the bottom spacer located below the gate electrode.

4. The vertical transistor of claim 1 , wherein the dielectric spacer further contains a horizontal air-gap, said horizontal air-gap is disposed below a bottommost surface of the gate electrode and is separated from the bottom source/drain region by the bottom spacer.

5. The vertical transistor of claim 4 , wherein the horizontal air-gap of the dielectric spacer is interconnected with the vertical air-gap of the dielectric spacer.

6. The vertical transistor of claim 1 , wherein the vertical air-gap present within the dielectric spacer is disposed below a topmost surface of the gate electrode.

7. The vertical transistor of claim 6 , wherein the vertical air-gap height is 30 to 95% of a height of the gate electrode.

8. The vertical transistor of claim 1 , wherein a distance between the gate electrode and the bottom source/drain contact is from 4 nm to 20 nm.

9. The vertical transistor of claim 1 , wherein the vertical air-gap height is from 15 nm to 50 nm and the vertical air-gap width is from 4 nm to 20 nm.

10. The vertical transistor of claim 1 , further comprising a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact.

11. A vertical transistor comprising:
a fin or nanowire disposed over a semiconductor substrate;
a gate electrode formed over sidewalls of the fin or nanowire;
a bottom source/drain contact adjacent to the gate electrode;
a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap;
a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact; and
a bottom source/drain region located between the fin or nanowire and a top semiconductor layer of the semiconductor substrate, wherein the conformal dielectric layer is separated from the bottom source/drain region by a bottom spacer.

12. The vertical transistor of claim 11 , further comprising a gate dielectric between the sidewall of the fin or the nanowire and the gate electrode, the gate dielectric extending below a bottommost surface of the gate electrode, wherein the conformal dielectric layer contacts a bottommost surface of the gate dielectric.

13. The vertical transistor of claim 1 , wherein the dielectric spacer comprises a dielectric material selected from the group consisting of amorphous carbon, a carbon-doped oxide, a fluorine-doped oxide, SiCOH and SiBCN.

14. The vertical transistor of claim 4 , wherein the horizontal air-gap height is from 4 nm to 20 nm and the horizontal air-gap width is from 30 nm to 50 nm.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Ning Tak H

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/021

  of air gaps · CPC title