Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-11615991-B2
Application number	US-202217705943-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	May 27, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

First claim

What is claimed is:

1. A method comprising:
depositing an inter-layer dielectric on a source/drain region and on a first unused region of a semiconductor fin, the source/drain region formed in the semiconductor fin;
forming a cut mask on the inter-layer dielectric, the cut mask comprising a first cut portion, a second cut portion, and a first trim portion, the semiconductor fin disposed between the first cut portion and the second cut portion in a top-down view, the first trim portion connecting the first cut portion to the second cut portion, the first trim portion overlapping the first unused region in the top-down view;
forming a line mask on the cut mask, the line mask comprising a first slot opening and a second slot opening, the first slot opening overlapping the source/drain region in the top-down view, the second slot opening overlapping the first trim portion in the top-down view;
etching a contact opening in the inter-layer dielectric using the line mask and the cut mask as a combined etching mask; and
forming a source/drain contact in the contact opening, the source/drain contact contacting the source/drain region.

2. The method of claim 1 further comprising:
forming a gate structure on a channel region of the semiconductor fin, the channel region disposed between the source/drain region and the first unused region.

3. The method of claim 1 , wherein the cut mask further comprises a second trim portion, the second trim portion connecting the first cut portion to the second cut portion, the second trim portion overlapping a second unused region of the semiconductor fin in the top-down view.

4. The method of claim 3 , wherein the first cut portion is separated from the second cut portion by a first distance, the first trim portion is separated from the second trim portion by a second distance, and the second distance is greater than the first distance.

5. The method of claim 3 , wherein the first cut portion is separated from the second cut portion by a first distance, the first trim portion is separated from the second trim portion by a second distance, and the second distance is less than the first distance.

6. The method of claim 3 , wherein the source/drain region is disposed between the first unused region and the second unused region.

7. The method of claim 1 , wherein the first cut portion, the second cut portion, and the first trim portion define a cut opening in the cut mask.

8. The method of claim 7 further comprising:
forming a masking layer on the inter-layer dielectric, the cut mask formed on the masking layer; and
patterning the masking layer by etching portions of the masking layer exposed by the first slot opening, the second slot opening, and the cut opening,
wherein etching the contact opening in the inter-layer dielectric comprises etching the portions of the inter-layer dielectric exposed by the masking layer.

9. A method comprising:
depositing an inter-layer dielectric on a source/drain region, a first dummy region of a semiconductor fin, and a second dummy region of the semiconductor fin, the source/drain region disposed between the first dummy region and the second dummy region;
forming a cut mask on the inter-layer dielectric, the cut mask comprising a first cut portion, a second cut portion, a first trim portion, and a second trim portion, the semiconductor fin disposed between the first cut portion and the second cut portion in a top-down view, the first trim portion and the second trim portion each connecting the first cut portion to the second cut portion, the first trim portion overlapping the first dummy region in the top-down view, the second trim portion overlapping the second dummy region in the top-down view;
patterning a contact opening in the inter-layer dielectric using the cut mask as an etching mask; and
forming a source/drain contact in the contact opening, the source/drain contact contacting the source/drain region.

10. The method of claim 9 , wherein the first cut portion is separated from the second cut portion by a first distance, the first trim portion is separated from the second trim portion by a second distance, and the second distance is greater than the first distance.

11. The method of claim 9 further comprising:
forming a line mask on the cut mask, the line mask comprising a slot opening, the slot opening overlapping the source/drain region in the top-down view.

12. The method of claim 11 , wherein the first cut portion, the second cut portion, the first trim portion, and the second trim portion define a cut opening in the cut mask, and a center of the cut opening is aligned with a center of the slot opening in the top-down view.

13. The method of claim 11 , wherein the slot opening exposes the first cut portion and the second cut portion.

14. The method of claim 11 , wherein the slot opening is a strip extending perpendicular to the semiconductor fin.

15. The method of claim 11 , wherein the first trim portion has a first width, the second trim portion has a second width, the slot opening has a third width, and the third width is less than the first width and the second width.

16. A device comprising:
a first fin extending from a semiconductor substrate;
a first source/drain region in the first fin;
a first metal gate on the first fin, the first metal gate disposed between the first source/drain region and a dummy region of the first fin;
a second fin extending from the semiconductor substrate;
a second source/drain region in the second fin;
a dielectric material on the first source/drain region, the second source/drain region, and the dummy region, the dielectric material physically contacting and extending continuously along the dummy region; and
a first source/drain contact extending through the dielectric material, the first source/drain contact physically contacting the first source/drain region and the second source/drain region.

17. The device of claim 16 further comprising:
a third source/drain region in the first fin; and
a second metal gate on the first fin, the second metal gate disposed between the third source/drain region and the dummy region of the first fin.

18. The device of claim 17 further comprising:
a first gate spacer adjacent the first metal gate; and
a second gate spacer adjacent the second metal gate, wherein no conductive features are disposed in a portion of the dielectric material disposed above the first fin and between the first gate spacer and the second gate spacer.

19. The device of claim 16 , wherein the first metal gate is on the second fin.

20. The device of claim 16 further comprising:
an inter-layer dielectric on the first source/drain contact and the first metal gate; and
a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact physically contacting the first source/drain contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien-Yuan
• Lin Jui-Ping
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/667

  by liquid etching only · CPC title