Integrated assemblies, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11514953-B2
Application number	US-202117243937-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	Aug 27, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a pair of adjacent memory-block-regions, the memory-block-regions comprising a first stack of alternating conductive levels and first insulative levels; and
a separator structure between the adjacent memory-block-regions, said separator structure comprising a second stack of alternating second and third insulative levels, the second insulative levels being substantially horizontally aligned with the conductive levels, and the third insulative levels being substantially horizontally aligned with the first insulative levels, the separator structure extending along a first direction and having a first region offset from a second region along the first direction, the first region comprising the second stack and the second region not comprising the second stack.

2. The integrated assembly of claim 1 comprising:
a conductive source structure under the memory-block-regions and under the separator structure;
first channel-material-pillars within the memory-block-regions and extending through the first stack to electrically couple with the source structure; and
second channel-material-pillars within the separator structure and extending through the second stack.

3. The integrated assembly of claim 2 wherein:
the first channel-material-pillars are along a first pitch along the first direction;
the second channel-material-pillars are along a second pitch along the first direction; and
the second pitch is greater than the first pitch.

4. The integrated assembly of claim 2 comprising one or more cell materials between the first channel-material-pillars and the first stack; and wherein the second insulative levels comprises said one or more cell materials.

5. The integrated assembly of claim 4 said one or more cell materials include silicon dioxide and silicon nitride.

6. The integrated assembly of claim 1 wherein the first and second regions have widths along a second direction orthogonal to the first direction, and wherein the second region is at least about 150% wider than the first region.

7. The integrated assembly of claim 1 wherein the second region comprises an insulative panel extending through the first stack.

8. An integrated assembly, comprising:
a pair of adjacent memory-block-regions, the memory-block-regions comprising a first stack of alternating conductive levels and first insulative levels; and
a separator structure between the adjacent memory-block-regions, said separator structure comprising a second stack of alternating second and third insulative levels, the second insulative levels being substantially horizontally aligned with the conductive levels, and the third insulative levels being substantially horizontally aligned with the first insulative levels; and
an SGD stack over the first and second stack, stacks; and wherein a first region of the separator structure being between the first and second memory-block-regions under the SGD stack.

9. The integrated assembly of claim 8 wherein the memory-block-regions are within a memory array region, wherein an SGD staircase region is laterally offset from the memory array region, with said SGD staircase region including the SGD stack over the first stack; and wherein the separator structure has a second region which extends through the first stack in the SGD staircase region.

10. The integrated assembly of claim 9 wherein the conductive levels include routing structures; wherein a routing structure staircase region is laterally offset from the SGD staircase region; wherein the routing structure staircase region includes the first stack; and wherein the separator structure has a third region which extends through the first stack in the routing structure staircase region.

11. The integrated assembly of claim 10 wherein the first region of the separator structure includes first bulbous regions alternating with first narrow regions, the second region of the separator structure includes second bulbous regions alternating with second narrow regions, and the third region of the separator structure includes third bulbous regions alternating with third narrow regions; and wherein the third bulbous regions are wider than the first bulbous regions.

12. The integrated assembly of claim 11 wherein the second bulbous regions are about a same width as the first bulbous regions.

13. The integrated assembly of claim 11 wherein the second bulbous regions are about a same width as the third bulbous regions.

14. The integrated assembly of claim 11 wherein the second bulbous regions are a different width than the first bulbous regions, and are a different width than the third bulbous regions.

15. The integrated assembly of claim 1 wherein the first stack includes at least two decks stacked one atop another.

16. An integrated assembly, comprising:
a first memory-block-region laterally between a first separator structure and a second separator structure;
a second memory-block-region laterally between the second separator structure and a third separator structure;
wherein the first and third separator structures are at least about 150% wider than the second separator structure;
wherein the first, second and third separator structures extend along a first direction;
wherein the first and third separator structures have substantially straight sidewalls along the first direction; and
wherein the second separator structure has serpentining sidewalls along the first direction.

17. The integrated assembly of claim 16 wherein the second separator structure includes bulbous regions alternating with narrow regions along the first direction.

18. The integrated assembly of claim 16 wherein the first and second memory-block-regions are within a memory array region; further comprising an SGD staircase region laterally offset from the memory array region and a routing structure staircase region laterally offset from the SGD staircase region; and wherein the first, second and third separator structures extend across the SGD staircase region and the routing structure staircase region.

19. The integrated assembly of claim 18 wherein the second separator structure has a first region within the memory array region, a second region within the SGD staircase region, and a third region within the routing structure staircase region; and wherein the second separator structure is wider within at least one of the second and third regions than within the first region.

20. The integrated assembly of claim 19 wherein the serpentining sidewalls of the second separator structure continue across the second and third regions.

21. The integrated assembly of claim 20 comprising projections of the first and third separator structures that extend beyond the routing structure staircase region, and wherein said projections have serpentining sidewalls.

22. The integrated assembly of claim 21 wherein the projections include bulbous regions alternating with narrow regions along the first direction.

23. The integrated assembly of claim 22 wherein the bulbous regions and narrow regions of the projections are first bulbous regions and first narrow regions; wherein the third region of the second separator structure has second bulbous regions alternating with second narrow regions along the first direction; and wherein the second bulbous regions are about a same width as the first bulbous regions.

24. The integrated assembly of claim 23 comprising a stack of alternating insu

Assignees

• Micron Technology Inc

Inventors

• Fukuzumi Yoshiaki
• Tessariol Paolo
• Wells David H
• Heineck Lars P
• Hill Richard J
• Xu Lifang
• Chary Indra V
• Camerlenghi Emilio

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L27/11556

  Electricity · mapped topic