Memory device

Patent metadata

Field	Value
Publication number	US-9673389-B2
Application number	US-201213357149-A
Country	US
Kind code	B2
Filing date	Jan 24, 2012
Priority date	Jan 24, 2012
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

First claim

What is claimed is:

1. A memory device comprising:
a first interconnect group in which a plurality of first interconnects is stacked, the first interconnect group including a plurality of first regions in which the first interconnects are formed along a first direction, and a second region in which a plurality of first contact plugs are formed on the first interconnects;
a plurality of second interconnects formed along a second direction different from the first direction, the first interconnects being stacked along the second direction; and
a memory cell including a variable-resistance-layer which is formed on a side surface of one of the second interconnects and is coupled with one of the first interconnects,
wherein in the second region, the first interconnect group includes a step portion, and the step portion includes a plurality of terraces,
adjacent terraces have different heights from each other by at least twice a distance between upper surfaces of two layers of the first interconnects which are included in the first interconnects and are adjacent in the second direction, and
the plurality of terraces of the second region of the first interconnect group are arranged along a third direction perpendicular to the first and second directions in at least two rows, the at least two rows being apart from each other with a separator interposed between the at least two rows, and the separator is higher than any one of the plurality of the terraces in height,
wherein a width of each of the terraces at a shorter side is larger than a width of each of the first interconnects in the first regions.

2. The device according to claim 1 , wherein the plurality of first interconnects formed on a same layer of one of the plurality of the first regions are connected in common, and are further connected to the second region.

3. The device according to claim 1 , further comprising:
a first insulating film formed on a side surface of the second region of the first interconnect group.

4. The device according to claim 3 , further comprising:
a second insulating film which covers the first regions of the first interconnect group,
wherein the first insulating film is formed by using a material having a large etching selectivity to the second insulating film.

5. The device according to claim 4 , wherein a main component of the first insulating film is SiN.

6. The device according to claim 1 , wherein the first contact plugs are coupled with a peripheral circuit through the second region, the peripheral circuit being formed on a layer lower than that of the memory cell is formed.

7. The device according to claim 1 , further comprising a selection element formed at an end of the bit line, the selection element including:
a drain region in contact with the end of the bit line,
a silicon layer in contact with the drain region,
a source region in contact with the silicon layer, wherein the bit line, the drain region, the silicon layer and the source region being arranged in line,
a gate insulating layer formed on a side of the silicon layer, the side being sandwiched by the drain region and the source region, and
a gate electrode formed on the gate insulating layer.

8. A memory device comprising:
a first interconnect group in which a plurality of first interconnects are stacked, the first interconnect group including a plurality of first regions in which the first interconnects are formed along a first direction, and a second region in which a plurality of first contact plugs are formed on the first interconnects;
a plurality of second interconnects formed along a second direction different from the first direction, the first interconnects being stacked along the second direction;
a memory cell including a variable-resistance-layer which is formed on a side surface of one of the second interconnects and is coupled with one of the first interconnects;
a plurality of memory cell regions in which the memory cells are arranged; and
a connection region in which the second region of the first interconnect group is provided and in which the first interconnects are coupled with a peripheral circuit via the first contact plugs,
wherein in the second region, the first interconnect group includes a step portion, and the step portion includes a plurality of terraces arranged in at least two rows, the at least two rows being apart from each other with a separator interposed between the at least two rows, and the separator is higher than any one of the plurality of the terraces in height,
adjacent terraces have different heights from each other by at least twice a distance between upper surfaces of two layers of the first interconnects which are included in the first interconnects and are adjacent in the second direction,
the connection region is provided between adjacent one of the memory cell regions, and
a width of each of the terraces at a shorter side is larger than a width of each of the first interconnects in the first regions.

9. The device according to claim 2 , wherein the connection region is located between the memory cell regions arranged in the first direction,
each of the first contact plugs is formed on each of the terraces, and
contact regions between the first contact plugs and the terraces are arranged in the third direction.

10. A memory device comprising:
a first interconnect group in which a plurality of first interconnects are stacked, the first interconnect group including a plurality of first region in which the first interconnects are formed along a first direction, and a second region in which a plurality of first contact plugs are formed on the first interconnects;
a plurality of second interconnects formed along a second direction different from the first direction, the first interconnects being stacked along the second direction;
a memory cell including a variable-resistance-layer which is formed on a side surface of one of the second interconnects and is coupled with one of the first interconnects;
a plurality of memory cell regions in which the memory cells are arranged; and
a connection region in which the second region of the first interconnect group is provided and in which the first interconnects are coupled with a peripheral circuit via the first contact plugs,
wherein in the second region, the first interconnect group includes a step portion, and the step portion includes a plurality of terraces,
adjacent terraces have different heights from each other by at least twice a distance between upper surfaces of two layers of the first interconnects which are included in the first interconnects and are adjacent in the second direction, and
the connection region is provided between adjacent ones of the memory cell regions,
wherein the connection region is located between the memory cell regions arranged in the first direction,
each of the first contact plugs is formed on each of the terraces, and
contact regions between the first contact plugs and the terraces are arranged in the third direction,
wherein the first interconnect group further includes a third region in which second contact plugs are formed on the first interconnects,
in the third region, the second contact plugs are formed on first ones of the first interconnects different from the first interconnects coupled with the first contact plugs in the second region,
in the third region, the first interconnect group includes a step portion, and
the step portion of the third region includes a plurality of terraces, and heights of the adjacent terraces are different from each other by the two or more first interconnects, and
wherein the second region is provided in parallel with the third region, and
the first inte

Assignees

• Murooka Kenichi
• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L45/1226

  Electricity · mapped topic

• H01L45/04 Primary

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic