Methods of fabricating three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9397114-B2
Application number	US-201213475023-A
Country	US
Kind code	B2
Filing date	May 18, 2012
Priority date	May 19, 2011
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

First claim

What is claimed is:

1. A method of fabricating a three-dimensional semiconductor, comprising:
forming a stack structure on a substrate, the stack structure including a plurality of insulating layers and a plurality of sacrificial layers, the insulating layers alternating with the sacrificial layers;
forming at least one first trench and a plurality of second trenches, the first and second trenches separating the stack structure into a plurality of mold structures, the at least one first trench between the second trenches;
forming first vertical insulating separators in the first and second trenches;
forming semiconductor patterns penetrating the mold structure, the semiconductor patterns being spaced apart from the first and second trenches;
removing the first vertical insulating separator from the second trench to expose the sacrificial layers;
removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separators; and
forming conductive patterns in the recess regions.

2. The method of claim 1 , wherein the forming first vertical insulating separators includes
forming a conformal etch stop layer covering surfaces inside the first and second trenches; and
forming an insulating gap-fill layer on the etch stop layer in the first and second trenches.

3. The method of claim 2 , wherein the etch stop layer includes an insulating material with etch selectivity to the sacrificial layers and the insulating layers.

4. The method of claim 2 , wherein the removing the sacrificial layers includes etching a sidewall of the etch stop layer to partially expose the insulating gap-fill layer.

5. The method of claim 2 , further comprising:
forming second vertical insulating separators filling the second trenches after the forming conductive patterns.

6. The method of claim 5 , wherein each of the second vertical insulating separators is a single layer formed of a different material than a material of the etch stop layer.

7. The method of claim 1 , wherein a width of the first trench is greater than a width of the second trench.

8. The method of claim 1 , wherein a horizontal width of each of the mold structures is substantially a same horizontal width.

9. The method of claim 1 , wherein the removing the first vertical insulating separator from the second trench includes
forming a mask pattern on the mold structures to cover the first trench and expose the second trenches; and
removing the first vertical insulating separator from each of the second trenches.

10. The method of claim 1 , further comprising:
forming a horizontal insulating layer to cover the recess regions before the forming conductive patterns, the horizontal insulating layer in contact with the semiconductor patterns and the first vertical insulating separators.

11. The method of claim 8 , further comprising:
forming a vertical insulating layer penetrating the mold structure before the forming semiconductor patterns,
wherein at least one of the vertical and horizontal insulating layers includes a data storing layer.

12. The method of claim 1 , wherein a horizontal width of each of the conductive patterns is a substantially same horizontal width as a corresponding one of the mold structures.

13. The method of claim 1 , further comprising:
forming a first doped region in the substrate below the first trench; and
forming a second doped region in the substrate below the second trench,
wherein the second doped region is a different conductivity type from the first doped region.

14. The method of claim 13 , wherein
the first doped region is a same conductivity type as the substrate, and
an impurity concentration of the first doped region is greater than an impurity concentration of the substrate.

15. A method of manufacturing a memory card, comprising:
forming a controller;
forming a semiconductor device, the forming a semiconductor device including the method of fabricating a three-dimensional semiconductor device of claim 1 ;
forming an interface; and
forming a bus connecting the controller, the semiconductor device, and the interface.

Assignees

• Yun Jumi
• Park Kwangmin
• Yoo Dongchul
• Jang Byong-Hyun
• Samsung Electronics Co Ltd

Inventors

• Yun Jumi
• Park Kwangmin
• Yoo Dongchul
• Jang Byong-Hyun

Classifications

• H10P14/60

  of insulating materials · CPC title

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic