3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Patent metadata

Field	Value
Publication number	US-9620514-B2
Application number	US-201514748575-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Sep 5, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate having a major surface;
a stack of alternating layers comprising insulating layers and control gate electrodes located over the substrate;
memory openings continuously extending from a topmost layer of the stack of alternating layers down to the major surface of the substrate, wherein each of the memory openings includes a respective memory stack structure extending through the stack of alternating layers, wherein sidewalls of the stack of alternating layers that physically contact the memory stack structures consist of concave sidewalls, wherein each of the memory stack structures comprises a plurality of memory cells arranged in a string extending in a first direction substantially perpendicular to the major surface of the substrate in a plurality of device levels, wherein each of the plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate;
at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells;
at least one second select gate electrode located above the plurality of memory cells;
a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface;
a first charge storage element located on a first side of the semiconductor channel; and
a second charge storage element located on a second side of the semiconductor channel and located at a same level as the first charge storage element, wherein the second charge storage element is electrically isolated from the first charge storage element, and located at a same level as the first charge storage element.

2. The memory device of claim 1 , wherein each memory cell of the plurality of memory cells comprises:
a unitary portion of the semiconductor channel;
the first charge storage element;
the second charge storage element;
at least a portion of a first control gate electrode located adjacent to the first charge storage element; and
at least a portion of a second control gate electrode located adjacent to the second charge storage element and electrically isolated from the first control gate electrode and the first charge storage element.

3. The memory device of claim 2 , wherein each memory cell of the plurality of memory cells further comprise:
a blocking dielectric contacting outer sidewalls of the first and second charge storage elements; and
a tunneling dielectric contacting inner sidewalls of the first and second charge storage elements and an outer sidewall of the semiconductor channel, such that the tunneling dielectric is located between the semiconductor channel and the first and second charge storage elements.

4. The memory device of claim 1 , wherein:
multiple sets of at least two charge storage elements located are around the semiconductor channel at each level of a respective control gate electrodes; and
the memory device further comprises separator insulator structures extending through the stack, contacting portions of an outer sidewall of the memory stack structure, and laterally separating the control gate electrodes of the plurality of charge storage elements, wherein the memory stack structure is located in a memory opening that includes a lateral recess region at each level of the control gate electrodes, wherein each set of at least two charge storage elements is located within a respective lateral recess region.

5. The memory device of claim 4 , wherein each set of at least two charge storage elements comprises at least two floating gates that are physically disjoined from one another.

6. The memory device of claim 4 , further comprising:
a single contiguous tunneling dielectric that laterally surrounds the semiconductor channel; and
a single contiguous blocking dielectric that contacts outer sidewalls of the respective single contiguous tunneling dielectric.

7. The memory device of claim 4 , wherein:
the memory device is a monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the three-dimensional array of NAND strings is located over another memory cell in a second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
each NAND string comprises:
the semiconductor channel in a respective memory stack structure, wherein at least one end portion of the semiconductor channel extends substantially perpendicular to a top surface of the silicon substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective semiconductor channel; and
the control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

8. The memory device of claim 4 , wherein:
the separator insulator structures comprise a subset of separator insulator structures that include sidewalls located entirely within a parallel pair of vertical surfaces extending along a first horizontal direction and spaced apart by a uniform distance along a second horizontal direction that is perpendicular to the first horizontal direction; and
each separator insulator structure within the subset of separator insulator structures is laterally spaced by a subset of the memory stack structures arranged along the first horizontal direction.

9. The memory device of claim 8 , wherein the separator insulator structures comprise a subset of separator insulator structures that include sidewalls located entirely within a parallel pair of vertical surfaces extending along a first horizontal direction and spaced apart by a uniform distance along a second horizontal direction that is perpendicular to the first horizontal direction.

10. The memory device of claim 8 , wherein each separator insulator structure within the subset of separator insulator structures is laterally spaced by a subset of the memory stack structures arranged along the first horizontal direction.

11. The memory device of claim 1 , wherein the first charge storage element and the second charge storage element are two spatially spaced-apart portions within a same memory material layer.

12. The memory device of claim 1 , wherein the first charge storage element is a portion of a first memory material layer, and the second charge storage element is a portion of a second memory material layer that is not in physical contact with the first memory material layer.

13. The memory device of claim 1 , wherein the major surface of the substrate is a topmost horizontal surface of a substrate semiconductor layer including a semiconductor material.

14. The memory device of claim 1 , wherein the portion of the semiconductor channel that extends vertically has an azimuthally modulated dopant profile in which a dopant concentration changes as a function of an azimuthal angle around a geometrical center of the portion of the semiconductor channel that extends vertically.

15. The memory device of claim 14 , further comprising:
separator insulator structures extending through the stack, contacting portions of an outer sidewall of the memory stack structure, an

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Kai James K
• Zhang Yanli
• Chien Henry
• Alsmeier Johann

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title