3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Patent metadata

Field	Value
Publication number	US-9728546-B2
Application number	US-201514748670-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Sep 5, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.

First claim

What is claimed is:

1. A memory device, comprising:
a stack of alternating layers comprising insulating layers and control gate electrodes located over a substrate;
a memory stack structure located within a memory opening extending through the stack and containing a semiconductor channel having a vertical portion that extends along a direction perpendicular to a top surface of the substrate;
a dielectric separator structure which is located between and electrically isolates first control gate electrodes from second control gate electrodes in each device level; and
at least one cell level isolation feature which electrically isolates lateral portions of a memory cell in each device level;
wherein:
the memory stack structure comprises at least two electrically isolated charge storage elements of the memory cell located around the semiconductor channel in each device level.

2. The memory device of claim 1 , wherein the at least one cell level isolation feature comprises the dielectric separator structure which contains a lateral stack, including from one side to another, a first dielectric liner comprising a first dielectric material, a dielectric fill material portion comprising a second dielectric material that is different from the first dielectric material, and a second dielectric liner comprising the first dielectric material.

3. The memory device of claim 2 , wherein:
the dielectric fill material portion is in contact with the vertical portion of the semiconductor channel;
the first dielectric liner and the second dielectric liner are in contact with the vertical portion of the semiconductor channel;
the first dielectric liner and the second dielectric liner have a same thickness; and
the dielectric fill material portion has a uniform thickness.

4. The memory device of claim 2 , wherein the first dielectric material comprises silicon nitride or silicon oxynitride, and the second dielectric material comprises silicon oxide.

5. The memory device of claim 2 , wherein the first dielectric material comprises silicon oxide, and the second dielectric material comprises silicon nitride or silicon oxynitride.

6. The memory device of claim 2 , wherein:
the separator structure extends through the stack of alternating layers, contacts sidewalls of the memory stack structure, and laterally separates the first and the second control gate electrodes;
the first dielectric liner contacts the first control gate electrodes;
the second dielectric liner contacts the second control gate electrodes; and the dielectric fill material portion is located between the first and the second liners.

7. The memory device of claim 2 , wherein the vertical portion of the semiconductor channel has a dopant concentration that either varies with an azimuthal angle or does not vary with the azimuthal angle within the vertical portion of the semiconductor channel as measured around a vertical axis passing through a geometrical center of the vertical portion of the semiconductor channel.

8. The memory device of claim 1 , wherein the at least one cell level isolation feature comprises the semiconductor channel which has an azimuthally modulated dopant profile in which a dopant concentration changes as a function of an azimuthal angle around a geometrical center of the vertical portion of the semiconductor channel.

9. The memory device of claim 8 , wherein:
the semiconductor channel has a plurality of alternating base doping semiconductor channel portions and enhanced doping semiconductor channel portions located in the same device level;
the enhanced doping semiconductor channel portions have a higher dopant concentration than the base doping semiconductor channel portions; and
the enhanced doping semiconductor channel portions face the respective separator structures while the base doping semiconductor channel portions face the respective control gate electrodes.

10. The memory device of claim 1 , wherein each charge storage element comprises a portion of a charge trapping dielectric layer.

11. The memory device of claim 1 , wherein:
each charge storage element comprises floating gate;
the separator structure is located between and electrically isolates a pair of floating gates located around the semiconductor channel in each device level;
the memory opening includes a lateral recess region in the control gate electrodes in each device level; and
each of the floating gates is located within a respective lateral recess region.

12. The memory device of claim 1 , wherein:
the memory device is a monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;
at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
each NAND string comprises:
a semiconductor channel, wherein an end portion of the semiconductor channel extends substantially perpendicular to a top surface of the silicon substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective semiconductor channel; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Serov Andrey
• Kai James K
• Zhang Yanli
• Chien Henry
• Alsmeier Johann

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic