Three-dimensional memory device having double-width staircase regions and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10615172-B2
Application number	US-201916363621-A
Country	US
Kind code	B2
Filing date	Mar 25, 2019
Priority date	May 11, 2018
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers with patterned stepped surfaces and an overlying retro-stepped dielectric material portion. The backside openings may be formed in rows with shape modifications in staircase regions to provide more lateral elongation in areas with lesser layers of the alternating stack. Non-circular horizontal cross-sectional shapes for the backside openings in the staircase regions allow formation of the backside opening with less shape distortion. Memory opening fill structures are formed in the memory openings, and the sacrificial material layers are replaced with electrically conductive layers using the backside openings as conduits for an etchant and for a deposition precursor material. The electrically conductive layers are isotropically recessed around each backside opening to form width-modulated cavities, which is filled with width-modulated insulating wall structures.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive strips located over a substrate;
a width-modulated insulating wall structure that laterally extends along a first horizontal direction and vertically extends through each layer in the alternating stack; and
groups of memory stack structures extending through the alternating stack,
wherein each insulating layer is a continuous perforated insulating layer that laterally extends around pillar structures of the width-modulated insulating wall structure along a second horizontal direction that is perpendicular to the first horizontal direction, and the width-modulated insulating wall structure includes a laterally alternating sequence of bulging regions and neck regions.

2. The three-dimensional memory device of claim 1 , further comprising a staircase region in which a first electrically conductive strip within the alternating stack has a greater lateral extent than a second electrically conductive strip within the alternating stack that underlies the first electrically conductive strip, wherein the segment of the laterally alternating sequence is located in the staircase region.

3. The three-dimensional memory device of claim 2 , wherein the groups of memory stack structures are located in a memory array region in which each layer of the alternating stack is present, and wherein a neck-to-neck distance between neighboring pairs of neck regions monotonically changes along a lengthwise direction of the width-modulated insulating wall structure within a nonuniform spacing segment of the laterally alternating sequence, and wherein the nonuniform spacing segment of the laterally alternating sequence is located in the staircase region.

4. The three-dimensional memory device of claim 3 , wherein the neck-to-neck distance between neighboring pairs of neck regions monotonically increases in the staircase region as a function of a lateral distance from the memory array region.

5. The three-dimensional memory device of claim 3 , wherein a ratio of a maximum neck-to-neck distance between neighboring pairs of neck regions and a minimum neck-to-neck distance between neighboring pairs of neck regions increases in the staircase region is at least two.

6. The three-dimensional memory device of claim 3 , wherein the neck-to-neck distance between neighboring pairs of neck regions has a uniform pitch within the memory array region.

7. The three-dimensional memory device of claim 6 , wherein:
memory stack structures within each group within the groups of memory stack structures are arranged in a two-dimensional array with a first periodicity along the first horizontal direction; and
the uniform pitch of the neck-to-neck distance between neighboring pairs of neck regions within the memory array region is the same as the first periodicity.

8. The three-dimensional memory device of claim 1 , wherein the electrically conductive strips in each vertical level of the alternating stack comprise discrete strips that are laterally spaced apart by the width-modulated insulating wall structure.

9. The three-dimensional memory device of claim 1 , wherein two electrically conductive strips in each laterally neighboring pair of electrically conductive strips that are located in a same vertical level are vertically spaced from the substrate by a same vertical distance, and are laterally spaced apart from each other by a laterally undulating portion of the width-modulated insulating wall structure.

10. The three-dimensional memory device of claim 9 , wherein:
the alternating stack includes respective stepped surfaces that extend from a bottommost layer to a topmost layer within a respective alternating stack; and
each of the electrically conductive strips includes a pair of laterally undulating lengthwise sidewalls that generally extend along the first horizontal direction and a straight widthwise sidewall that is located at the stepped surfaces and that extends along a second horizontal direction that is perpendicular to the first horizontal direction.

11. The three-dimensional memory device of claim 10 , further comprising:
a retro-stepped dielectric material portion that contacts each straight widthwise sidewall of the electrically conductive strips, or is laterally spaced from each straight widthwise sidewall of the electrically conductive strips by a respective backside blocking dielectric layer; and
discrete insulating pillars that vertically extend through the retro-stepped dielectric material portion.

12. The three-dimensional memory device of claim 11 , wherein:
the retro-stepped dielectric material portion overlies the stepped surfaces of the alternating stack;
each of the laterally undulating lengthwise sidewalls of the electrically conductive strips includes a plurality of concave vertical sidewalls that are adjoined to one another along vertical edges; and
each of the plurality of concave vertical sidewalls contacts a respective convex vertical sidewall of the width-modulated insulating wall structure.

13. The three-dimensional memory device of claim 1 , wherein the width-modulated insulating wall structure comprises:
ribbed beams laterally contacting a respective pair of electrically conductive strips and located at each level of the electrically conductive strips and continuously extending along the first horizontal direction; and
pillar structures contacting a respective pair of an overlying ribbed beam and an underlying ribbed beam and arranged along the first horizontal direction and laterally spaced apart from each other.

14. The three-dimensional memory device of claim 13 , wherein:
each ribbed beam laterally contacting the respective pair of electrically conductive strips has a sidewall located with a same flat vertical plane that includes sidewalls of the respective pair of electrically conductive strips that laterally extend along the second horizontal direction; and
for each pair of an overlying ribbed beam and an underlying ribbed beam, the underlying ribbed beam has a greater lateral extent along the first horizontal direction than the overlying ribbed beam.

15. The three-dimensional memory device of claim 14 , wherein:
each group of memory stack structures includes rows of memory stack structures that are arranged along the first horizontal direction with a first pitch; and
the ribbed beams have a variable width along the second horizontal direction that changes periodically with translation along the first horizontal direction, wherein a periodicity of modulation of the variable width is the same as the first pitch.

Assignees

• Sandisk Technologies Llc

Inventors

• Nagata Koichiro
• Kanazawa Junpei
• Otsu Yoshitaka
• Iwai Takaaki
• Minagawa Shuji
• Otoi Hisakazu

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H10W20/0698

  Local interconnections · CPC title