Monolithic three-dimensional NAND strings and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9576975-B2
Application number	US-201514957762-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Aug 26, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a vertically repeating stack of unit layer stacks, each unit layer stack comprising an electrically conductive layer, a lower silicon oxide material layer overlying the electrically conductive layer, a dielectric fill material region overlying the lower silicon oxide material layer, and an upper silicon oxide material layer overlying the dielectric fill material region;
a semiconductor channel extending through the vertically repeating stack, at least one end portion of the semiconductor channel extending substantially perpendicular to a top surface of a substrate;
charge storage regions that are located at each level of the electrically conductive layers, laterally surrounding the semiconductor channel, and vertically spaced from one another;
a tunneling dielectric laterally surrounding the semiconductor channel, wherein an inner sidewall of each charge storage region contacts a respective portion of an outer sidewall of the tunneling dielectric; and
a continuous blocking dielectric layer that contacts each lower silicon oxide material layer, each upper silicon oxide material layer, and each dielectric fill material region, each charge storage region, and the tunneling dielectric,

wherein:
the continuous blocking dielectric layer comprises:
a plurality of laterally protruding portions in contact with an outer sidewall of a respective charge storage region, and
a plurality of laterally recessed portions extending between a respective pair of laterally protruding portions and contacting a respective portion of the outer sidewall of the tunneling dielectric;

the plurality of laterally recessed portions comprises a silicon oxynitride in which an atomic concentration of nitrogen atoms is greater than 0.1%; and
the plurality of laterally protruding portions comprises a silicon oxide material in which an atomic concentration of nitrogen atoms is less than 100 parts per million.

2. The monolithic three-dimensional memory device of claim 1 , wherein each surface of the charge storage regions is in physical contact with the continuous blocking dielectric layer or the tunneling dielectric.

3. The monolithic three-dimensional memory device of claim 1 , wherein the dielectric fill material region consists of a dielectric material portion having a homogenous composition and does not include any cavity.

4. The monolithic three-dimensional memory device of claim 1 , wherein the dielectric fill material region comprises a cavity that is free of a solid material and is encapsulated by a dielectric material.

5. The monolithic three-dimensional memory device of claim 1 , wherein each charge storage region has an annular shape, a vertical inner sidewall, and a vertical outer sidewall.

6. The monolithic three-dimensional memory device of claim 1 , wherein:
the charge storage regions comprise silicon nitride; and
the semiconductor channel comprises a polycrystalline silicon-containing semiconductor material.

7. The monolithic three-dimensional memory device of claim 1 , wherein the dielectric fill material regions are portions of a contiguous dielectric fill material layer that contacts sidewalls of each electrically conductive layer, each lower silicon oxide layer, and each upper silicon oxide layer within the vertically repeating stack.

8. The monolithic three-dimensional memory device of claim 1 , wherein each of the dielectric fill material regions comprises:
a first vertically protruding portion that contacts a sidewall of a respective upper silicon oxide material layer; and
a second vertically protruding portion that contacts a sidewall of a respective lower silicon oxide material layer.

9. The monolithic three-dimensional memory device of claim 1 , wherein the unit layer stack further comprises a backside blocking dielectric comprising a dielectric metal oxide and contacting a top surface, a bottom surface, and a sidewall surface of a respective electrically conductive layer.

10. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device comprises a vertical NAND device located in a device region;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; and
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Kai James
• Makala Raghuveer S
• Liu Jin
• Chowdhury Murshed
• Huang Camilla
• Alsmeier Johann

Classifications

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L21/7682

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic