Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereof

Patent metadata

Field	Value
Publication number	US-10373969-B2
Application number	US-201815865892-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Jan 9, 2018
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.

First claim

What is claimed is:

1. A method of operating a three-dimensional memory device comprising a stack of alternating insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the stack in a vertical direction perpendicular to the layers and the substrate, wherein:
each of the memory stack structures comprises a memory film that surrounds a vertical semiconductor channel;
the electrically conductive layers comprise drain select gate electrode layers located over word line electrically conductive layers;
the memory stack structures are arranged in multiple groups that are spaced apart from each other in a horizontal direction by drain select level isolation structures that each extend in the vertical direction through the drain select gate electrode layers dividing each drain select gate electrode layer into horizontal drain select gate electrode layer sections;
within each group of memory stack structures, at least one row of memory stack structures is arranged, each of the memory stack structures in the at least one row is only partially surrounded by a respective drain select gate electrode layer section due to each of the memory stack structures in the at least one row also directly contacting a respective one of the drain select level isolation structures;
applying a target string bias voltage to a selected drain select gate electrode layer section, which partially surrounds a first row of memory stack structures in a respective group of memory stack structures, wherein each of the memory stack structures of the first row is in direct contact with a first one of the drain select isolation structures; and
applying a neighboring string bias voltage, which has a greater magnitude than the target string bias voltage, to a first unselected drain select gate electrode layer section that neighbors the selected drain gate electrode layer section and contacts the first one of the drain select level isolation structures.

2. The method of claim 1 , wherein:
a selected memory stack structure is located in the first row of memory stack structures, and directly contacts the first one of the drain select isolation structures;

the selected memory stack structure is located in a selected group of the multiple groups;
the first unselected drain select gate electrode layer section is located in a first neighboring group that is adjacent to the selected group and that is separated from the selected group by the first one of the drain select isolation structures;
the selected drain select gate electrode layer section partially surrounds the selected memory stack structure in a drain select level;
electrical charge is injected into a first portion of a memory film in the selected memory stack structure that contacts the selected drain select gate electrode layer section by the target string bias voltage; and
electrical charge is injected into a second portion of the memory film in the select memory stack structure that contacts the first one of the drain select isolation structures by the neighboring string bias voltage.

3. The method of claim 2 , further comprising:
applying a pass bias voltage to a second unselected drain select gate electrode layer section that is laterally spaced from the selected drain select gate electrode layer section by at least the first neighboring group; and
applying a programming drain bias voltage to a drain region which contacts a vertical semiconductor channel within the selected memory stack structure,
wherein the neighboring string bias voltage greater than the pass bias voltage.

4. The method of claim 3 , wherein:
the neighboring string bias voltage is in a range from 101% to 150% of the target string bias voltage; and
the pass bias voltage is in a range from 20% to 50% of the target string bias voltage.

5. The method of claim 3 , wherein:
the target string bias voltage is in a range from 9 V to 30 V;
the neighboring string bias voltage is in a range from 9.5 V to 45 V;
the pass bias voltage is in a range from 3 V to 22.5 V; and
the programming drain bias voltage is in a range from −1 V to 2 V.

6. The method of claim 2 , wherein the three-dimensional memory device further comprises:
drain regions contacting a top end of a respective one of the vertical semiconductor channels; and
bit lines that are electrically shorted to a respective subset of the drain regions such that each bit line is electrically shorted to only one drain region per each neighboring pair of strings groups, and each bit line is electrically shorted to more than one drain region in each memory block.

7. The method of claim 6 , further comprising applying a neighboring string inhibit voltage to each bit line electrically connected to vertical semiconductor channels that pass through the first unselected drain select gate electrode layer section during charge injection into the memory film of the selected memory stack structure, wherein a voltage difference between the neighboring string inhibit voltage and the pass bias voltage is less than a critical voltage that induces charge tunneling through memory films within the memory stack structures.

8. The method of claim 7 , wherein:
the selected drain select gate electrode layer section contacts a second one of the drain select level isolation structures;
an additional first unselected drain select gate electrode layer section contacts the second one of the drain select level isolation structures; and
the method further comprises applying the neighboring string inhibit voltage to each bit line electrically connected to vertical semiconductor channels that pass through the additional first unselected drain select gate electrode layer section during charge injection into the memory film within the selected memory stack structure.

9. The method of claim 7 , further comprising applying a selected string inhibit voltage to each bit line connected to vertical semiconductor channels of unselected memory stack structures that pass through the selected drain select gate electrode layer section, wherein the selected string inhibit voltage is greater than the programming drain bias voltage and prevents charge tunneling within the unselected memory stack structures.

10. The method of claim 7 , further comprising applying the programming drain bias voltage each bit line connected to vertical semiconductor channels of additional memory stack structures that pass through the selected drain select gate electrode layer section.

11. The method of claim 2 , wherein charge trapping is induced within the portions of the memory film in the selected memory stack structure that are located at the drain select level while word line electrically conductive layers among the electrically conductive layers are electrically biased at a voltage that does not induce charge tunneling through the memory film in the selected memory stack structure.

12. The method of claim 11 , further comprising storing electrical charges in memory elements within the memory film in the selected memory stack structure in a subsequent programming operation or reading electrical charges in memory elements within the memory film in the selected memory stack structure in a subsequent reading operation.

13. The method of claim 1 , wherein:
the three-dimensional memory device further comprises a pair of dielectric material portions that laterally extend along an additional horizontal direction and that are located on either side of the stack to separate a selected memory block containing the selected memory group and the neighboring memory group from adjacent memory blocks;
the word

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Zhang Peng
• Alsmeier Johann
• Dong Yingda

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11578

  Electricity · mapped topic