Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017103992-A1
Application number	US-201615046674-A
Country	US
Kind code	A1
Filing date	Feb 18, 2016
Priority date	Oct 7, 2015
Publication date	Apr 13, 2017
Grant date	—

Abstract

An embodiment comprises: a memory cell array that includes a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of first conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; a cover layer that covers at least some of side surfaces of each of the plurality of first conductive layers; and a second conductive layer commonly connected to ends of some of the plurality of first conductive layers. Moreover, the commonly connected ends of some of the plurality of first conductive layers and the second conductive layer are connected without being interposed by the cover layer.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of first conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; a cover layer that covers at least some of side surfaces of each of the plurality of first conductive layers; and a second conductive layer commonly connected to ends of some of the plurality of first conductive layers, wherein the commonly connected ends of some of the plurality of first conductive layers and the second conductive layer are connected without being interposed by the cover layer.

2 . The semiconductor memory device according to claim 1 , further comprising
a wiring line portion including the plurality of first conductive layers, wherein the wiring line portion comprises a first stepped portion whose height decreases with increasing distance from the memory cell array.

3 . The semiconductor memory device according to claim 1 , wherein
the plurality of first conductive layers to which the second conductive layer is commonly connected include a lowermost layer of the plurality of first conductive layers.

4 . The semiconductor memory device according to claim 1 , wherein
the plurality of first conductive layers to which the second conductive layer is commonly connected include an uppermost layer of the plurality of first conductive layers.

5 . The semiconductor memory device according to claim 1 , further comprising
a third conductive layer disposed between the second conductive layer and the semiconductor substrate.

6 . The semiconductor memory device according to claim 1 , wherein
some of the plurality of first conductive layers function as a drain side select gate line, some of the plurality of first conductive layers function as a source side select gate line, and the second conductive layer is provided to each of the drain side select gate line and the source side select gate line.

7 . The semiconductor memory device according to claim 1 , wherein
the second conductive layer has a stepped structure whose height decreases with increasing distance from the memory cell array.

8 . The semiconductor memory device according to claim 2 , further comprising
a second stepped portion that has a structure in which a plurality of first layers and second layers are stacked alternately in the stacking direction on the semiconductor substrate, is disposed facing the first stepped portion, and has a height that increases with increasing distance from the memory cell array, wherein a portion facing the second conductive layer of the second stepped portion has a length in a direction of increasing distance from the memory cell array which is substantially identical.

9 . The semiconductor memory device according to claim 1 , further comprising
a contact connected to the second conductive layer, wherein the plurality of first conductive layers commonly connected to the second conductive layer are electrically connected to the contact via the second conductive layer.

10 . A method of manufacturing a semiconductor memory device, the semiconductor memory device including: a memory cell array that includes a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; and a wiring line portion that includes the plurality of conductive layers, the method comprising:
alternately stacking a plurality of inter-layer insulating layers and first sacrifice layers on the semiconductor substrate; forming a first gap that penetrates at least some of the plurality of inter-layer insulating layers and at least two layers of the first sacrifice layers; depositing a second sacrifice layer inside the first gap; alternately stacking a plurality of the inter-layer insulating layers and the first sacrifice layers on the second sacrifice layer; dividing the plurality of inter-layer insulating layers and the plurality of first sacrifice layers by a first etching to form a first portion and a second portion, the first portion including at its end the second sacrifice layer; and replacing the plurality of first sacrifice layers and the second sacrifice layer included in the first portion to form the plurality of conductive layers.

11 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising:
when replacing the plurality of first sacrifice layers and the second sacrifice layer included in the first portion to form the plurality of conductive layers, removing the first sacrifice layer to form a second gap and removing the second sacrifice layer to form a third gap; and depositing a cover layer at a boundary of the second gap and the third gap and the plurality of inter-layer insulating layers.

12 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising
performing a plurality of times of etchings on the plurality of first sacrifice layers included in the first portion to form a first stepped portion whose height decreases with increasing distance from the memory cell array.

13 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising
performing a plurality of times of etchings on the plurality of first sacrifice layers and the second sacrifice layer included in the first portion to form a second stepped portion whose height decreases with increasing distance from the memory cell array.

14 . The method of manufacturing a semiconductor memory device according to claim 12 , comprising
when performing the etching, aligning a length in a direction of increasing distance from the memory cell array of the second sacrifice layer.

15 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising:
the first gap being formed such that at least one layer of the first sacrifice layers is left below the second sacrifice layer; and after the first etching, performing a second etching that causes recession of ends of layers located in a higher layer than the first sacrifice layer below the second sacrifice layer.

16 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising:
causing some of the plurality of conductive layers to function as a drain side select gate line; causing some of the plurality of conductive layers to function as a source side select gate line; and providing the second conductive layer to each of the drain side select gate line and the source side select gate line.

17 . The method of manufacturing a semiconductor memory device according to claim 10 , comprising
performing a plurality of times of etchings on the second portion, and forming a third stepped portion that faces the wiring line portion and has a height that increases with increasing distance from the memory cell array.

18 . The method of manufacturing a semiconductor memory device according to claim 17 , comprising
aligning a length in a direction of increasing closeness to the memory cell array, of a portion facing the second sacrifice layer, of the third stepped portion.

Assignees

• Toshiba Kk

Inventors

• HACHISUGA Ayaha
• Ichinose Daigo

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title