Multi-state programming for non-volatile memory

Patent metadata

Field	Value
Publication number	US-9595317-B2
Application number	US-201514929156-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	May 28, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.

First claim

The invention claimed is:

1. A method comprising:
programming a memory cell coupled to a bit line by:
programming the memory cell to an intermediate data state from an erased state; and
programming the memory cell from the intermediate data state to a target data state by biasing the bit line to one of a plurality of bit line bias voltages, the bit line bias voltage determined based on the target data state,

wherein the bit line bias voltage is based on a voltage difference between an intermediate state distribution and the target state distribution.

2. The method of claim 1 , further comprising:
programming the memory cell to one of a plurality of intermediate data states from the erased state; and
programming the memory cell from the one of a plurality of intermediate data states to the target data state by biasing the bit line to the one of a plurality of bit line bias voltages.

3. The method of claim 1 , further comprising programming a second memory cell coupled to a second bit line by programming the second memory cell from the erased state to a second target data state by biasing the second bit line to one of a plurality of second bit line bias voltages, the second bit line bias voltage determined based on the second target data state.

4. The method of claim 1 , wherein a number of the plurality of bit line bias voltages equals a number of data states that may be stored in the memory cell.

5. The method of claim 1 , wherein the plurality of bit line bias voltages comprises four bit line bias voltages.

6. The method of claim 1 , wherein the plurality of bit line bias voltages comprises a first bit line bias voltage of about 0V, a second bit line bias voltage of about 0.4V, a third bit line bias voltage of about 0.8V, and a fourth bit line bias voltage of about 1.2V.

7. The method of claim 1 , wherein the non-volatile memory comprises a two-dimensional or a three-dimensional non-volatile memory.

8. A non-volatile memory comprising:
a bit line;
a memory cell coupled to the bit line; and
a controller configured to program the memory cell to a target data state by biasing the bit line to one of a plurality of bit line bias voltages, the bit line bias voltage determined based on the target data state,
wherein the bit line bias voltage is based on a voltage difference between an intermediate state distribution and a target state distribution.

9. The non-volatile memory of claim 8 , wherein:
the non-volatile memory further comprises a sense amplifier coupled to the bit line and the controller; and
the controller is further configured to cause the sense amplifier to bias the bit line to the one of a plurality of bit line bias voltages.

10. The non-volatile memory of claim 9 , wherein the controller is further configured to:
program the memory cell from an erased state to an intermediate data state; and
program the memory cell from the intermediate data state to the target data state by biasing the bit line to the one of a plurality of bit line bias voltages.

11. The non-volatile memory of claim 8 , wherein the controller is further configured to program the memory cell from an erased state to the target data state by biasing the bit line to the one of a plurality of bit line bias voltages.

12. The non-volatile memory of claim 8 , wherein a number of the plurality of bit line bias voltages equals a number of data states that may be stored in the memory cell.

13. The non-volatile memory of claim 8 , wherein the plurality of bit line bias voltages comprises four bit line bias voltages.

14. The non-volatile memory of claim 8 , wherein the plurality of bit line bias voltages comprises a first bit line bias voltage of about 0V, a second bit line bias voltage of about 0.4V, a third bit line bias voltage of about 0.8V, and a fourth bit line bias voltage of about 1.2V.

15. The non-volatile memory of claim 8 , wherein the non-volatile memory comprises a two-dimensional or a three-dimensional non-volatile memory.

16. A sense amplifier comprising:
a first circuit coupled to a bit line of a memory cell, the first circuit configured to bias the bit line to a first bit line bias voltage to inhibit the memory cell from being programmed; and
a second circuit coupled to the bit line of the memory cell, the second circuit configured to bias the bit line to a second bit line bias voltage to program the memory cell,
wherein the second bit line bias voltage is one of a plurality of bit line bias voltages, the second bit line bias voltage configured based on a target data state of the memory cell, and
wherein the second bit line bias voltage is based on a voltage difference between an intermediate state distribution and a target state distribution.

17. The sense amplifier of claim 16 , wherein the second circuit comprises:
an input terminal coupled to an input signal voltage;
a first transistor comprising a first threshold voltage, a first control terminal coupled to the input terminal, and a second terminal; and
a second transistor comprising a second threshold voltage, a second control terminal coupled to the second terminal and a third terminal coupled to the bit line,
wherein the second bit line bias voltage equals the input signal voltage minus the first threshold voltage and the second threshold voltage.

18. The sense amplifier of claim 16 , wherein a number of the plurality of bit line bias voltages equals a number of data states that may be stored in the memory cell.

19. The sense amplifier of claim 16 , wherein the plurality of bit line voltages comprises four bit line voltages.

20. The sense amplifier of claim 16 , wherein the plurality of bit line voltages comprises a first bit line bias voltage of about 0V, a second bit line bias voltage of about 0.4V, a third bit line bias voltage of about 0.8V, and a fourth bit line bias voltage of about 1.2V.

21. The sense amplifier of claim 16 , wherein the non-volatile memory comprises a two-dimensional or a three-dimensional non-volatile memory.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Li Yen-Lung
• Cernea Raul-Adrian
• Yuh Jong Hak
• Tseng Tai-Yuan

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/107

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/24

  Bit-line control circuits · CPC title