Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9305637-B2
Application number	US-201414194781-A
Country	US
Kind code	B2
Filing date	Mar 2, 2014
Priority date	Sep 9, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising:
a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein; and
a control circuit configured to perform a writing operation on the memory cells of the memory cell array,
wherein the writing operation performed on a memory cell in an erasure state includes a pre-programming verification operation to determine a threshold level of the memory cell in the erasure state and a program operation in which a program voltage for the memory cell is selected from a plurality of program voltages based on a determination result of the pre-programming verification operation, wherein
the control circuit selects and writes a first program voltage to a memory cell which is determined to have a threshold level larger than a reference value in the pre-programming verification operation, and selects and writes a second program voltage lower than the first program voltage to a memory cell which is determined to have a threshold level smaller than the reference value in the pre-programming verification operation.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein
the control circuit performs the pre-programming verification operation while loading data into the control circuit from an external device.

3. The nonvolatile semiconductor memory device according to claim 2 , wherein
the control circuit includes a first latch circuit and a second latch circuit, and
the first latch circuit holds data read from the memory cell in the pre-programming verification operation, and the second latch circuit holds data which is loaded into the control circuit from the external device.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein
each memory cell is connected to between a word line and a bit line, and
the control circuit selects a voltage applied to a bit line connected to a memory cell based on the determination result of the pre-programming verification operation performed on the memory cell.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the writing operation further includes a verification operation and a program-after-verification operation that is performed when the verification operation indicates that the program operation has failed.

6. The nonvolatile semiconductor memory device according to claim 5 , wherein the program voltage applied during the program-after-verification operation is larger than the program voltage applied during the program operation by a difference value and the difference value varies based on the determination result of the pre-programming verification operation.

7. The nonvolatile semiconductor memory device according to claim 1 , wherein the writing operation performed on the memory cell in the erasure state is a lower page writing operation.

8. A nonvolatile semiconductor memory device comprising:
a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein; and
a control circuit configured to perform a writing operation on the memory cells of the memory cell array,
wherein the writing operation performed on a memory cell in an erasure state includes a pre-programming verification operation to determine a threshold level of the memory cell in the erasure state, a pre-program operation in which the threshold level of the memory cell in the erasure state is increased if the threshold level of the memory cell in the erasure state is below a reference level and is maintained if the threshold level of the memory cell in the erasure state is above the reference level, and a program operation.

9. The nonvolatile semiconductor memory device according to claim 8 , wherein
the control circuit performs the pre-programming verification operation while loading data into the control circuit from an external device.

10. The nonvolatile semiconductor memory device according to claim 9 , wherein
the control circuit includes a first latch circuit and a second latch circuit, and
the first latch circuit holds data read from the memory cell in the pre-programming verification operation, and the second latch circuit holds data which is loaded into the control circuit from the external device.

11. The nonvolatile semiconductor memory device according to claim 8 , wherein
each memory cell is connected to between a word line and a bit line, and
the control circuit selects a voltage applied to a bit line connected to a memory cell based on a determination result of the pre-programming verification operation performed on the memory cell.

12. The nonvolatile semiconductor memory device according to claim 8 , wherein the writing operation performed on the memory cell in the erasure state is a lower page writing operation.

13. A nonvolatile semiconductor memory device comprising:
a memory cell array having a plurality of bit lines and word lines and nonvolatile memory cells at intersections of the bit lines and word lines, each memory cell having one of a plurality of threshold values programmed therein; and
a control circuit configured to perform a writing operation on the memory cells of the memory cell array,
wherein the writing operation performed on a memory cell in an erasure state includes a pre-programming verification operation to determine a threshold level of the memory cell in the erasure state, and a program operation in which a bit line voltage for the memory cell is selected from a plurality of bit line voltages based on a determination result of the pre-programming verification operation, wherein
the control circuit selects a first bit line voltage to a memory cell which is determined to have a threshold level larger than a reference value in the pre-programming verification operation, and selects a second bit line voltage lower than the first bit line voltage to a memory cell which is determined to have a threshold level smaller than the reference value in the pre-programming verification operation.

14. The nonvolatile semiconductor memory device according to claim 13 , wherein
the control circuit selects and writes a first program voltage to a memory cell which is determined to have a threshold level larger than the reference value in the pre-programming verification operation, and selects and writes a second program voltage lower than the first program voltage to a memory cell which is determined to have a threshold level smaller than the reference value in the pre-programming verification operation.

15. The nonvolatile semiconductor memory device according to claim 13 , wherein
the control circuit performs the pre-programming verification operation while loading data into the control circuit from an external device.

16. The nonvolatile semiconductor memory device according to claim 13 , wherein the writing operation performed on the memory cell in the erasure state is a lower page writing operation.

Assignees

• Toshiba Kk

Inventors

• Funatsuki Rieko
• Futatsuyama Takuya
• Arai Fumitaka

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title