Programming memories with multi-level pass signal

Patent metadata

Field	Value
Publication number	US-2016307622-A1
Application number	US-201615189178-A
Country	US
Kind code	A1
Filing date	Jun 22, 2016
Priority date	Jul 18, 2014
Publication date	Oct 20, 2016
Grant date	—

Abstract

Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.

First claim

What is claimed is:

1 . A method of operating a memory, comprising:
applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation; applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation; applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage; and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.

2 . The method of claim 1 , wherein the multi-step pass voltage is applied to an access line coupled to control gates of the plurality of memory cells selected for the programming operation, the method further comprising applying the multi-step pass voltage to an other memory cell having a control gate coupled to the access line.

3 . The method of claim 2 , further comprising applying the particular voltage level to a data line coupled to the other memory cell prior to applying the voltage level of the certain step of the multi-step pass voltage.

4 . The method of claim 2 , further comprising applying a second multi-step pass voltage to a second plurality of memory cells having control gates coupled to a different access line, wherein each memory cell of the plurality of memory cells selected for the programming operation is connected in series with a respective memory cell of the second plurality of memory cells.

5 . The method of claim 4 , wherein a voltage level of each step of the multi-step pass voltage is a same voltage level as a corresponding step of the second multi-step pass voltage.

6 . The method of claim 1 , wherein the particular step of the multi-step pass voltage is a last step of the multi-step pass voltage, and wherein the certain step of the multi-step pass voltage is selected from a group consisting of any step of the multi-step pass voltage from an initial step of the multi-step pass voltage to a step of the multi-step pass voltage immediately prior to the last step of the multi-step pass voltage.

7 . The method of claim 1 , wherein the multi-step pass voltage is applied to an access line coupled to control gates of the plurality of memory cells selected for the programming operation, the method further comprising applying a second multi-step pass voltage to a second plurality of memory cells having control gates coupled to a different access line, wherein each memory cell of the plurality of memory cells selected for the programming operation is connected in series with a respective memory cell of the second plurality of memory cells.

8 . The method of claim 1 , further comprising verifying whether any memory cells of the plurality of memory cells selected for the programming operation have reached a threshold voltage level corresponding to a respective target data state after applying the programming pulse.

9 . The method of claim 1 , wherein applying the programming pulse after applying the voltage level of the particular step of the multi-step pass voltage comprises applying the programming pulse having a voltage level higher than the voltage level of a last step of the multi-step pass voltage.

10 . The method of claim 1 , further comprising:
applying a second multi-step pass voltage to the plurality of memory cells selected for the programming operation; applying a second programming pulse for the programming operation to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the second multi-step pass voltage to the plurality of memory cells selected for the programming operation; applying the particular voltage level to any data lines coupled to a third subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the second multi-step pass voltage; and applying the particular voltage level to any data lines coupled to a fourth subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the second multi-step pass voltage.

11 . The method of claim 10 , wherein the first subset of memory cells comprises memory cells selected for programming to a particular target data state, wherein the second subset of memory cells comprises memory cells selected for programming to a different target data state.

12 . The method of claim 11 , wherein the certain step of the multi-step pass voltage is an initial step of the multi-step pass voltage, wherein the certain step of the second multi-step pass voltage is an initial step of the second multi-step pass voltage, wherein the third subset of memory cells comprises the first subset of memory cells and memory cells of the second subset of memory cells that reached the different target data state prior to applying the second multi-step pass voltage, and wherein the fourth subset of memory cells comprises memory cells of the second subset of memory cells that did not reach the different target data state prior to applying the second multi-step pass voltage.

13 . The method of claim 12 , wherein the third subset of memory cells further comprises memory cells of additional subsets of memory cells of the plurality of memory cells selected for the programming operation that reached respective target data states of those additional subsets of memory cells prior to applying the second multi-step pass voltage.

14 . A method of operating a memory, comprising:
boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse; and boosting the channel voltage of the memory cell selected for programming to a second voltage level, lower than the particular voltage level, for a programming pulse subsequent to the particular programming pulse.

15 . The method of claim 14 , wherein boosting the channel voltage of the memory cell for the particular programming pulse comprises raising a voltage level applied to an access line coupled to a control gate of the memory cell while a certain voltage level is applied to a data line coupled to the memory cell, and wherein boosting the channel voltage of the memory cell for the particular programming pulse occurs after raising the voltage level applied to the access line coupled to the control gate of the memory cell while a voltage level lower than the certain voltage level is applied to the data line.

16 . The method of claim 14 , wherein the memory cell is a first memory cell and further comprising:
boosting a channel voltage of a second memory cell selected for programming to a fourth voltage level for a second particular programming pulse; and boosting the channel voltage of the second memory cell selected for programming to a fifth voltage level, higher than the fourth voltage level, for a programming pulse subsequent to the second particular programming pulse; wherein the fourth voltage level is higher than the particular voltage level; wherein the fifth voltage level is higher than the second voltage level; and wherein the second me

Assignees

• Micron Technology Inc

Inventors

• Raghunathan Shyam Sunder
• Kalavade Pranav
• Parat Krishna K
• Srinivasan Charan

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title