Programming memories with stepped programming pulses

Patent metadata

Field	Value
Publication number	US-9767894-B2
Application number	US-201414299074-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jun 9, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.

First claim

What is claimed is:

1. A method of programming a memory device, comprising:
applying a plurality of programming pulses to an access line coupled to a control gate of each of a plurality of cells of the memory device to be programmed, wherein each programming pulse of the plurality of programming pulses comprises a first portion that contributes towards programming a first cell of the plurality of cells to a first data state of a plurality of data states and a second portion subsequent to the first portion that contributes towards programming a second cell of the plurality of cells to a second data state of the plurality of data states, wherein the first portion of each programming pulse of the plurality of programming pulses has a higher voltage than the second portion of each programming pulse of the plurality of programming pulses.

2. The method of claim 1 , wherein the first data state is associated with a first threshold voltage level and the second data state is associated with a second threshold voltage level, wherein the first threshold voltage level is higher than the second threshold voltage level.

3. The method of claim 2 , wherein the first portion that contributes towards programming the first cell of the plurality of cells to the first data state moves a threshold voltage of the first cell towards the first threshold voltage level, wherein second portion that contributes towards programming the second cell of the plurality of cells to the second data state moves a threshold voltage of the second cell towards the second threshold voltage level.

4. The method of claim 1 , wherein the second cell is inhibited from programming during the first portion of the programming pulse.

5. The method of claim 4 , wherein the second cell being inhibited from programming during the first portion of the programming pulse comprises boosting a channel voltage of the second cell during the first portion of the programming pulse.

6. A method of programming a multi-level memory, comprising:
programming first cells towards a first threshold voltage using a first portion of a programming pulse that is applied to an access line;
after programming the first cells towards the first threshold voltage using the first portion of the programming pulse that is applied to the access line, programming second cells towards a second threshold voltage lower than the first threshold voltage using a second portion of the programming pulse that is applied to the access line having a voltage level lower than the first portion of the programming pulse that is applied to the access line;
wherein the access line to which the programming pulse is applied is coupled to a control gate of each of the first memory cells and each of the second memory cells.

7. The method of claim 6 , wherein the first threshold voltage is in a highest threshold voltage distribution.

8. A memory device, comprising:
an array of memory cells; and
a controller configured to cause a plurality of programming pulses to be applied to an access line coupled to a control gate of each of plurality of cells of the memory device to be programmed, wherein each programming pulse of the plurality of programming pulses comprises a first portion that is to move a threshold voltage of a first cell of the plurality of cells towards a first threshold voltage level associated with a first data state and a second portion subsequent to the first portion that is to move a threshold voltage of a second cell of the plurality of cell towards a second threshold voltage level associated with a second data state, wherein the first portion of each programming pulse of the plurality of programming pulses has a higher voltage than the second portion of each programming pulse of the plurality of programming pulses.

9. A memory device, comprising:
an array of memory cells; and
a controller configured to program first cells towards a first threshold voltage using a first portion of a programming pulse applied to an access line, and after programming the first cells towards the first threshold voltage using the first portion of the programming pulse applied to the access line, to program second cells towards a second threshold voltage lower than the first threshold voltage using a second portion of the programming pulse applied to the access line having a voltage level lower than the first portion of the programming pulse applied to the access line;
wherein the access line to which the programming pulse is applied is coupled to a control gate of each of the first memory cells and each of the second memory cells.

10. The memory device of claim 9 , wherein the first threshold voltage is in a highest threshold voltage distribution.

11. A method of programming a plurality of memory cells, comprising:
programming a first memory cell of the plurality of memory cells towards a first programmed data state during a first portion of a stepped programming pulse applied to an access line; and
after programming the first memory cell of the plurality of memory cells towards the first programmed data state during the first portion of the stepped programming pulse, programming a second memory cell of the plurality of memory cells towards a second programmed data state during a second portion of the stepped programming pulse;
wherein the first portion of the stepped programming pulse is at a higher voltage level than the second portion of the stepped programming pulse; and
wherein the access line is coupled to a control gate of each of the plurality of memory cells.

12. The method of claim 11 , further comprising:
inhibiting the second memory cell from programming responsive to the first portion of the stepped programming pulse; and
inhibiting the first memory cell from programming responsive to the second portion of the stepped programming pulse.

13. The method of claim 12 , wherein the first programmed data state is associated with a threshold voltage level that is higher than a threshold voltage level associated with the second programmed data state.

14. The method of claim 13 , further comprising programming a third memory cell of the plurality of memory cells towards a third programmed data state during the first portion of the stepped programming pulse, wherein the third programmed data state is associated with a threshold voltage level that is higher than the threshold voltage level associated with the second programmed data state.

15. The method of claim 14 , further comprising:
programming a fourth memory cell of the plurality of memory cells towards a fourth programmed data state and programming a fifth memory cell of the plurality of memory cells towards a fifth programmed data state during the first portion of the stepped programming pulse, wherein the fourth programmed data state is associated with a threshold voltage level that is higher than the threshold voltage level associated with the third programmed data state, and wherein the fifth programmed data state is associated with a threshold voltage level that is higher than the threshold voltage level associated with the fourth programmed data state.

16. The method of claim 14 , further comprising:
inhibiting the third memory cell from programming responsive to the second portion of the stepped programming pulse; and
inhibiting a fourth memory cell of the plurality of memory cells from programming responsive to the stepped programming pulse, wherein the fourth memory cell is in an erased data state.

17. The method of claim 16 , wherein:
inhibiting the second memory cell from programming responsive to the fi

Assignees

• Micron Technology Inc

Inventors

• Tang Qiang
• Guo Xiaojiang
• Ghodsi Ramin

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title