Memory cells using multi-pass programming

Patent metadata

Field	Value
Publication number	US-9530504-B2
Application number	US-201514743755-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Jun 23, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells.

First claim

The invention claimed is:

1. A method for programming non-volatile memory cells, the non-volatile memory cells accessible by a plurality of word lines, the method comprising:
using a four-pass programming technique to program a block of the non-volatile memory cells,
wherein for each of a first three programming passes of the four-pass programming technique, each of the memory cells comprises an overlapping threshold distribution.

2. The method of claim 1 , wherein the non-volatile memory cells comprise multi-level memory cells.

3. The method of claim 1 , wherein each of the non-volatile memory cells stores a lower page data, a middle page data and an upper page data.

4. The method of claim 1 , wherein the four-pass programming technique comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

5. The method of claim 1 , wherein the four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

6. The method of claim 1 , wherein the four-pass programming technique comprises a first fine programming operation and a second fine programming operation.

7. The method of claim 1 , wherein after a fourth programming pass each of the memory cells comprises a non-overlapping threshold distribution.

8. The method of claim 1 , wherein the four-pass programming technique comprises a first programming operation that narrows a threshold voltage distribution of the memory cells, and a second programming operation that further narrows a threshold voltage distribution of the memory cells.

9. The method of claim 1 , wherein the non-volatile memory cells comprise two-dimensional NAND memory cells.

10. The method of claim 1 , wherein the non-volatile memory cells comprise three-dimensional NAND memory cells.

11. A non-volatile memory comprising:
an array of memory cells organized into blocks wherein memory cells of each block are erasable together and are accessible by a plurality of word lines; and
a controller for operating a program operation comprising:
using a four-pass programming technique to program a block of the memory cells,
wherein for each of a first three programming passes of the four-pass programming technique, each of the memory cells comprises an overlapping threshold distribution.

12. The non-volatile memory of claim 11 , wherein the non-volatile memory cells comprise multi-level memory cells.

13. The non-volatile memory of claim 11 , wherein each of the non-volatile memory cells stores a lower page data, a middle page data and an upper page data.

14. The non-volatile memory of claim 11 , wherein the four-pass programming technique comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

15. The non-volatile memory of claim 11 , wherein the four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

16. The non-volatile memory of claim 11 , wherein the four-pass programming technique comprises a first fine programming operation and a second fine programming operation.

17. The non-volatile memory of claim 11 , wherein after a fourth programming pass each of the memory cells comprises a non-overlapping threshold distribution.

18. The non-volatile memory of claim 11 , wherein the four-pass programming technique comprises a first programming operation that narrows a threshold voltage distribution of the memory cells, and a second programming operation that further narrows a threshold voltage distribution of the memory cells.

19. The non-volatile memory of claim 11 , wherein the non-volatile memory comprises a two-dimensional NAND memory.

20. The non-volatile memory of claim 11 , wherein the non-volatile memory comprise a three-dimensional NAND memory.

21. A non-volatile storage system comprising:
a silicon substrate;
a plurality of non-volatile storage elements monolithically formed in one or more physical levels of an array of memory cells having active areas disposed above the silicon substrate; and
one or more managing circuits, above or within the substrate, in communication with the non-volatile storage elements to use a four-pass programming technique to program a block of the non-volatile memory cells,
wherein for each of a first three programming passes of the four-pass programming technique, each of the memory cells comprises an overlapping threshold distribution.

22. The non-volatile storage system of claim 21 , wherein the memory cells comprise multi-level memory cells.

23. The non-volatile storage system of claim 21 , wherein each of the memory cells stores a lower page data, a middle page data and an upper page data.

24. The non-volatile storage system of claim 21 , wherein the four-pass programming technique comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

25. The non-volatile storage system of claim 21 , wherein the four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

26. The non-volatile storage system of claim 21 , wherein the four-pass programming technique comprises a first fine programming operation and a second fine programming operation.

27. The non-volatile storage system of claim 21 , wherein after a fourth programming pass each of the memory cells comprises a non-overlapping threshold distribution.

28. The non-volatile storage system of claim 21 , wherein the four-pass programming technique comprises a first programming operation that narrows a threshold voltage distribution of the memory cells, and a second programming operation that further narrows a threshold voltage distribution of the memory cells.

29. The non-volatile storage system of claim 21 , wherein the non-volatile storage system comprises two-dimensional NAND memory.

30. The non-volatile storage system of claim 21 , wherein the non-volatile memory comprises three-dimensional NAND memory.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lei Bo
• Hemink Gerrit Jan
• Higashitani Masaaki
• Wan Jun
• Zhou Zhenming

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title