Semiconductor memory device including multi-level cell and programming method thereof

Patent metadata

Field	Value
Publication number	US-9859014-B2
Application number	US-201615212559-A
Country	US
Kind code	B2
Filing date	Jul 18, 2016
Priority date	Feb 4, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to perform a program operation on the memory cell array;
a control logic configured to control the peripheral circuit to program the memory cell array; and
one or more programs, wherein the one or more programs are configured to be executed by the control logic, the programs including instructions for:
setting first verify voltages for one or more target program states;
programming memory cells coupled to a selected word line using the first verify voltages, each of the memory cells being to be programmed to the one or more target program states;
determining whether the programming of all the memory cells coupled to the selected word line has passed or not;
setting second verify voltages for the one or more target program states, after the programming of all the memory cells coupled to the selected word line has passed; and
re-programming the memory cells coupled to the selected word line using the second verify voltages,
wherein at least one of the second verify voltages is higher than a corresponding verify voltage of the first verify voltages, and
at least another one of the second verify voltages is equal to a corresponding verify voltage of the first verify voltages.

2. The semiconductor memory device of claim 1 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, include a program state of which threshold voltage level is the lowest among a plurality of program states.

3. The semiconductor memory device of claim 1 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, are one or more program states of which threshold voltage levels are relatively low among a plurality of program states.

4. The semiconductor memory device of claim 1 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, are program states that unintentionally change in subsequent program operations with respect to the one or more other target program states.

5. The semiconductor memory device of claim 1 , wherein the memory cell array includes a plurality of pages each including the plurality of memory cells, and the control logic perform the re-programming on the memory cells included in predetermined pages among the plurality of pages.

6. The semiconductor memory device of claim 5 , wherein the predetermined pages are pages including memory cells adjacent to drain select transistors of the memory cell array.

7. The semiconductor memory device of claim 5 , wherein the predetermined pages are a page including memory cells adjacent to the drain select transistors of the memory cell array and a page including memory cells adjacent to source select transistors of the memory cell array.

8. The semiconductor memory device of claim 1 , wherein re-programming the memory cells to the one or more target program states includes programming the memory cells, which have been programmed to threshold voltages lower than the one or more target program states, to a threshold voltage distribution of the one or more target program states after the program operation of the memory cells is completed.

9. A method of operating a semiconductor memory device, the method comprising:
providing a page including a plurality of memory cells;
programming the memory cells included in the page using first verify voltages for one or more target program states, each of the memory cells being to be programmed to the one or more target program states;
setting second verify voltages for one or more target program states; and
programming the memory cells included in the page using the second verify voltages,
wherein at least one of the second verify voltages is higher than a corresponding verify voltage of the first verify voltages, and
at least another one of the second verify voltages is equal to a corresponding verify voltage of the first verify voltages.

10. The method of claim 9 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, include a program state of which threshold voltage level is lower than the one or more other target program states.

11. The method of claim 9 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, are one or more program states of which threshold voltage levels are relatively lower than the one or more other target program states.

12. The method of claim 9 , wherein the one or more target program states, each of whose second verify voltage is higher than a corresponding first verify voltage, are program states that unintentionally change in subsequent program operations with respect to the one or more other target program states.

13. The method of claim 9 , wherein programming the memory cells included in the page using first verify voltages include:
applying a program voltage to the memory cells; and
performing a program verification operation on the memory cells, using the first verify voltages,
wherein at least one of the first verify voltages is lower than a threshold voltage distribution of a corresponding program state of the one or more target program states.

14. The method of claim 13 , wherein programming the memory cells included in the page using first verify voltages includes:
applying the program voltage to the memory cells; and
performing the program verification operation on the memory cells, using the second verify voltages,
wherein at least one of the second verify voltages is higher than the corresponding verify voltage of the first verify voltages.

15. A method of operating a semiconductor memory device, the method comprising:
providing a plurality of pages each including a plurality of memory cells;
programming the plurality of memory cells included in the plurality of pages using first verify voltages for one or more target program states, each of the plurality of memory cells being to be programmed to the one or more target program states;
setting second verify voltages for one or more target program states; and
programming the memory cells included in the pages using the second verify voltages,
wherein at least one of the second verify voltages is higher than a corresponding verify voltage of the first verify voltages, and
at least another one of the second verify voltages is equal to a corresponding verify voltage of the first verify voltages.

16. The method of claim 15 , wherein the pages except predetermined pages are programmed using a normal program method.

17. The method of claim 15 , wherein predetermined pages include one or more pages adjacent to source select transistors among the plurality of pages.

18. The method of claim 15 , wherein predetermined pages include at least one page adjacent to drain select transistors and at least one page adjacent to the source select transistors among the plurality of pages.

19. The method of claim 15 , wherein the one or more target program states include a program state of which threshold voltage level is lower than the one or more other target program states.

20. The method of claim 15 , wherein programming the plurality of memory cells included in the plurality of pages using firs

Assignees

• Sk Hynix Inc

Inventors

• Park Min Sang
• Kim Sung Ho
• Lee Kyong Taek
• Lee Yun Bong
• Choi Gil Bok

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title