Programming multibit memory cells

Patent metadata

Field	Value
Publication number	US-9685233-B2
Application number	US-201414153934-A
Country	US
Kind code	B2
Filing date	Jan 13, 2014
Priority date	Jan 16, 2013
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.

First claim

The invention claimed is:

1. A method of operating a multiple bits per cell memory, comprising:
storing a data set for programming a plurality of multi-level memory cells, the data set including for multi-level memory cells in the plurality of multi-level memory cells corresponding multi-bit codes indicating one of a plurality of program states or an inhibit state, where the plurality of program states correspond to a corresponding plurality of program level targets for the multi-level memory cells; and
executing a plurality of program cycles for the plurality of multi-level memory cells to program the plurality of multi-level memory cells to program states in the plurality of program states, wherein a program cycle in the plurality of program cycles includes:
(i) applying a program bias to a set of multi-level memory cells in the plurality of multi-level memory cells for which the corresponding multi-bit codes indicate one of the plurality of program states, and
(ii) after applying the program bias, applying program verify steps to the set of multi-level memory cells, including a program verify step for each multi-level memory cell in the set applying one or more program level targets determined by the corresponding multi-bit codes and updating the corresponding multi-bit codes in the data set based upon program level targets at which the multi-level memory cells pass,

wherein the plurality of multi-level memory cells are configured in a plurality of stacked layers, including grouping multi-level memory cells into a plurality of groups, where a first group of memory cells includes a first set of layers and a second group of memory cells includes a second set of layers;
wherein the memory includes a plurality of pages of memory cells, and a page includes memory cells coupled to a set of N bit lines and to a set of M word lines, the plurality of multi-level memory cells includes memory cells in a selected page coupled in common to one word line, and the multi-level memory cells in respective stacked layers in the plurality of stacked layers are connected to bit lines in the set of N bit lines; and
including programming a page of memory cells by performing said storing and said executing for successive pluralities of multi-level memory cells, in an order that includes selecting the page, selecting memory cells in the selected page in the first group, and then selecting in sequence each word line in the page, and then selecting memory cells in the selected page in the second group, and then selecting in sequence each word line in the page.

2. The method of claim 1 , wherein the multi-level memory cells comprise charge trapping memory cells, and the program level targets are threshold voltage levels.

3. The method of claim 1 , wherein executing the plurality of program cycles includes a sequence of program cycles which incrementally increase program levels of the multi-level memory cells in the plurality of program states.

4. The method of claim 1 , wherein executing the plurality of program cycles includes at least one program cycle that includes applying only one program verify step for one of the plurality of program level targets.

5. The method of claim 1 , wherein executing the plurality of program cycles includes at least one program cycle that includes applying multiple program verify steps, including a program verify step for each one of the plurality of program level targets.

6. The method of claim 1 , including changing the program bias during the plurality of cycles.

7. The method of claim 1 , wherein the program bias applied in the program cycle includes a word line voltage applied to a word line coupled in common to the plurality of multi-level memory cells, and a selected one of program enable bias and a program inhibit bias applied to bit lines coupled to the plurality of memory cells.

8. The method of claim 1 , including using a preliminary programming sequence before applying the plurality of program cycles.

9. The method of claim 8 , wherein the preliminary programming sequence includes one or more preliminary program cycles, wherein a preliminary program cycle includes applying a preliminary program bias to multi-level memory cells in the plurality of program states, and after applying the preliminary program bias, applying one or more pre-program verify steps at a preliminary program level or preliminary program levels.

10. The method of claim 8 , wherein the preliminary programming sequence includes executing a plurality of preliminary program cycles including at least one preliminary program cycle that includes applying a preliminary program bias to multi-level memory cells in one of the plurality of program states, and after applying the preliminary program bias applying multiple program verify steps, including a pre-program verify step for each one of a plurality of preliminary program levels.

11. The method of claim 10 , wherein the pre-program verify step for each one of the plurality of program levels includes applying a different pre-program verify voltage for each one of the plurality of preliminary program levels.

12. The method of claim 10 , wherein the pre-program verify step for each one of the plurality of program levels includes applying a first pre-program verify voltage for one or more of plurality of preliminary program levels, and a second pre-program verify voltage for one of plurality of preliminary program levels having a highest target threshold, and wherein the second pre-program verify voltage is set to verify the program level target of a highest threshold program state.

13. The method of claim 1 , wherein the memory includes a plurality of pages of memory cells, and a page includes memory cells coupled to a set of N bit lines and to a set of M word lines, and the plurality of multi-level memory cells includes memory cells in a selected page coupled in common to one word line.

14. The method of claim 13 , including programming the page of memory cells in an order that includes selecting the page, and then selecting in sequence each word line in the page.

15. The method of claim 14 , wherein the memory comprises strings of memory cells each string coupled on one end to one of the N bit lines by a first select switch and coupled to a source of reference voltage on another end by a second switch, and the step of selecting in sequence each word line in the page includes starting with a memory cell on the string nearest to the first switch and proceeding in order down the string to the memory cell on the string nearest to the second switch.

16. The method of claim 1 , wherein the plurality of groups includes at least three groups, and the bit lines in each group are separated by at least two other bit lines in two different groups of layers.

17. A method of operating a multiple bits per cell memory, comprising:
storing a data set for programming a plurality of multi-level memory cells, the data set including multi-bit codes indicating one of a plurality of program states or an inhibit state for corresponding multi-level memory cells in the plurality of multi-level memory cells, where the plurality of program states correspond to a corresponding plurality of program level targets for the multi-level memory cells; and
executing a plurality of program cycles for the plurality of multi-level memory cells to program the plurality of multi-level memory cells to program level targets in the plurality of program level targets indicated by initial values of the multi-bit codes, wherein a program cycle in the plurality of program cycles includes:
(i) applying

Assignees

• Macronix Int Co Ltd

Inventors

• Hsieh Chih-Chang
• Chen Ti-Wen
• Li Yung Chun
• Chang Kuo-Pin

Classifications

• G11C2211/5621

  Multilevel programming verification · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11551

  Electricity · mapped topic

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• H01L27/11578

  Electricity · mapped topic