Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same

Patent metadata

Field	Value
Publication number	US-10892019-B2
Application number	US-202016788638-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	Mar 12, 2018
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory block including a plurality of memory cells disposed in a vertical direction; and
a control circuit configured to apply an erase voltage to an erase source terminal of the memory block, and configured to apply a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the memory block as an erase target block.

2. The nonvolatile memory device of claim 1 , wherein:
the control circuit is configured to apply a second voltage to a second selection line among the plurality of selection lines,
the second voltage is lower than the erase voltage, and
the second selection line is disposed farther from the erase source terminal than the first selection line and is used for selecting the memory block as the erase target block.

3. The nonvolatile memory device of claim 1 , wherein:
the memory block is divided into a first sub-block and a second sub-block in the vertical direction,
the control circuit is configured to apply the first voltage or a second voltage to a second selection line among the plurality of selection lines based on a location relationship between the erase source terminal and the first sub-block,
the second voltage is lower than the erase voltage, and
the second selection line is disposed farther from the erase source terminal than the first selection line and is used for selecting the first sub-block as an erase target sub-block.

4. A method of erasing data in a memory block within the nonvolatile memory device, comprising:
applying a non-zero erase voltage to a drain terminal a first string selection transistor within a vertical NAND string of memory cells comprising at least two string selection transistors;
applying a first voltage having a magnitude greater than the erase voltage to a first string selection line associated with the first string selection transistor; and
applying a non-zero second voltage having a magnitude less than the erase voltage to a second string selection line associated with a second string selection transistor below the first string selection transistor within the vertical NAND string of memory cells.

5. The method of claim 4 , wherein the source of the first string selection transistor is electrically connected to a drain of the second string selection transistor; wherein said applying the first voltage commences prior to said applying the non-zero erase voltage; and wherein said applying the non-zero erase voltage commences prior to said applying a non-zero second voltage.

6. A method of operating a nonvolatile memory device, comprising:
erasing data within a NAND string of memory cells within the nonvolatile memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string, by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors.

7. The method of claim 6 , wherein the pair of selection transistors are a pair of string selection transistors or a pair of ground selection transistors.

8. The method of claim 7 , wherein a source of a first one of the pair of selection transistors is electrically connected to a drain of a second one of the pair of selection transistors.

9. The method of claim 6 , wherein the first voltage has a magnitude greater than the erase voltage and the second voltage has a magnitude less than the erase voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Kwak Dong-Hun
• Yoon Chi-Weon

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title