U-shaped common-body type cell string

Patent metadata

Field	Value
Publication number	US-9893084-B2
Application number	US-201715422853-A
Country	US
Kind code	B2
Filing date	Feb 2, 2017
Priority date	Apr 16, 2013
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising at least three U-shaped flash cell strings in a memory cell region and a peripheral transistor in a periphery of the semiconductor device, each U-shaped flash cell string comprising a bottom pass transistor, the method comprising for each of the at least three U-shaped flash cell strings:
forming a bottom pass transistor of a respective U-shaped flash cell string in the memory cell region, the bottom pass transistor for the respective U-shaped flash cell string extending in a word line direction that is substantially perpendicular to a bit line direction; and
forming a first vertical portion and a second vertical portion of the respective U-shaped flash cell string, the bottom pass transistor of the respective U-shaped flash cell string being comprised in a horizontal portion of the respective U-shaped flash cell string joining the first vertical portion and the second vertical portion,
wherein the at least three U-shaped flash cell strings are formed concurrently,
wherein the at least three U-shaped flash cell strings are formed adjacent to each other so as to be aligned in the bit line direction, and
wherein the bottom pass transistors of the at least three U-shaped flash cell strings are formed concurrently with the peripheral transistor, such that a gate electrode of the bottom pass transistor for each of the at least three U-shaped flash cell strings is isolated from gate electrodes of the other bottom pass transistors.

2. The method of claim 1 , wherein forming the bottom pass transistor of each respective U-shaped flash cell string comprises:
forming a gate dielectric layer of the bottom pass transistor on the top surface of a semiconductor substrate; and
forming the gate electrode of the bottom pass transistor directly on the gate dielectric such that only the gate dielectric is intervening between the gate electrode of the bottom pass transistor and the top surface of the semiconductor substrate.

3. The method of claim 1 , further comprising:
patterning a semiconductor substrate in the memory cell region into a plurality of active island patterns separated from each other by trenches; and
wherein each of the at least three U-shaped flash cell strings is formed on one of the plurality of active island patterns.

4. The method of claim 2 , further comprising:
forming a well implant region in the semiconductor substrate in the memory cell region, wherein the gate dielectric layer of the bottom pass transistor for each of the at least three U-shaped flash cell strings is formed on the well implant region such that in an on-state of the bottom pass transistor, a conductive channel is formed within the semiconductor substrate underneath the gate electrode of the bottom pass transistor.

5. The method of claim 1 ,
wherein the semiconductor device is a NAND flash device.

6. The method of claim 1 , further comprising:
forming memory cells for data storage in the first and the second vertical portion for each U-shaped flash cell string, wherein the first vertical portion and the second vertical portion of each U-shaped flash cell string are formed as pillar-shaped portions, and the horizontal portion being free of memory cells.

7. The method of claim 6 , further comprising:
depositing a layer of silicon in each of the pillar-shaped portions.

8. The method of claim 6 , further comprising:
filling an innermost part of each of the pillar-shaped portions with a dielectric material.

9. The method of claim 6 , further comprising:
depositing a charge trap layer in each of the pillar-shaped portions.

10. The method of claim 6 , wherein the memory cells include floating gates.

Assignees

• Conversant Intellectual Property Man Inc

Inventors

• Rhie Hyoung Seub

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title