Sub-block erase

Patent metadata

Field	Value
Publication number	US-9620217-B2
Application number	US-201514668790-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Aug 12, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

First claim

The invention claimed is:

1. A method of operating a NAND array that includes a plurality of blocks of memory cells, wherein a block of memory cells in the plurality of blocks comprises a plurality of NAND strings having channel lines between first string select switches and second string select switches, and in which the plurality of NAND strings shares a set of word lines between the first and second string select switches, comprising:
applying a channel-side erase voltage to the channel lines of the NAND strings through the first string select switches in a selected block;
applying word line-side erase voltages to a selected subset of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, the selected subset including more than one member of the set of word lines;
inhibiting tunneling in memory cells coupled to an unselected subset of the set of word lines shared by NAND strings in the selected block, the unselected subset including more than one member of the set of word lines;
applying a first control voltage to turn on word line drivers for word lines in the selected subset; and
applying a second control voltage to turn off word line drivers for word lines in the unselected subset, when applying a global word line voltage matching the second control voltage to inputs of the word line drivers for word lines in the unselected subset,
wherein the first control voltage is different than the second control voltage.

2. The method of claim 1 , wherein said inhibiting includes floating word lines in the unselected subset when applying the channel-side erase voltage.

3. The method of claim 1 , comprising:
applying a bias voltage on a boundary word line in the set of word lines, to induce boundary conditions, between the selected subset on one side of the boundary word line and the unselected subset on another side of the boundary word line.

4. The method of claim 3 , wherein the boundary conditions include electric fields for generation of holes.

5. The method of claim 3 , comprising:
applying a third control voltage to turn on a word line driver for the boundary word line when applying the bias voltage on the boundary word line,
wherein the third control voltage is between the first control voltage and the second control voltage.

6. The method of claim 1 , wherein the channel lines include a drain side with an N+ type terminal connected to the first string select switches, and a source side with a P+ type terminal connected to the second string select switches, comprising:
applying a source-side voltage to the source side of the channel lines, providing holes to the channel lines, and raising a channel potential along the channel lines.

7. The method of claim 1 , comprising:
executing said applying a channel-side erase voltage, said applying word line-side erase voltages, and said inhibiting, in response to a command to erase memory cells coupled to the selected subset of the set of word lines in the selected block.

8. A method of operating a NAND array that includes a plurality of blocks of memory cells, wherein a block of memory cells in the plurality of blocks comprises a plurality of NAND strings having channel lines between first string select switches and second string select switches, and in which the plurality of NAND strings shares a set of word lines between the first and second string select switches, comprising:
applying a channel-side erase voltage to the channel lines of the NAND strings through the first string select switches in a selected block;
applying word line-side erase voltages to a selected subset of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, the selected subset including more than one member of the set of word lines; and
inhibiting tunneling in memory cells coupled to an unselected subset of the set of word lines shared by NAND strings in the selected block, the unselected subset including more than one member of the set of word lines, including
applying a control voltage to turn on word line drivers for word lines in the selected subset; and
applying the control voltage to turn off word line drivers for word lines in the unselected subset, when applying a global word line voltage matching the control voltage to inputs of the word line drivers for word lines in the unselected subset.

9. The method of claim 8 , comprising:
applying a bias voltage on a boundary word line in the set of word lines, to induce boundary conditions, between the selected subset on one side of the boundary word line and the unselected subset on another side of the boundary word line;
applying the control voltage to turn on a word line driver for the boundary word line,
wherein the bias voltage is between the word line-side erase voltage and the global word line voltage.

10. A memory, comprising:
a NAND array that includes a plurality of blocks of memory cells, wherein a block of memory cells in the plurality of blocks comprises a plurality of NAND strings having channel lines between first string select switches and second string select switches, and in which the plurality of NAND strings shares a set of word lines between the first and second string select switches;
a set of local word line drivers driving respective word lines in the set of word lines in a selected block, including a first subset of the set of local word line drivers driving the first subset of the set of word lines, a second subset of the set of local word line drivers driving the second subset of the set of word lines, and a boundary word line driver driving a boundary word line in the set of word lines between the first subset of the set of word lines and the second subset of the set of word lines;
a set of global word lines, including first global word lines connected to the first subset of the set of local word line drivers, and a second global word line connected to the boundary word line driver; and
a controller coupled to the memory cells in the selected block, including:
logic to apply a channel-side erase voltage to the channel lines of the NAND strings through the first string select switches in the selected block;
logic to apply word line-side erase voltages to a first subset of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the first subset, the first subset including more than one member of the set of word lines; and
logic to inhibit tunneling in memory cells coupled to a second subset of the set of word lines shared by NAND strings in the selected block, the second subset including more than one member of the set of word lines.

11. The memory of claim 10 , wherein the first global word lines are connected to the second subset of the set of local word line drivers, including a first global word line driver driving the first global word lines.

12. The memory of claim 10 , wherein the set of global word lines includes third global word lines connected to the second subset of the set of local word line drivers, including a first global word line driver driving the first global word lines, and a third global word line driver driving the third global word lines.

13. The memory of claim 10 , the controller including:
logic to apply a first global word line voltage on the first global word lines;
logic to apply a first control voltage to turn on the first subset of the set of local word line drivers, providing the word line-side erase voltages; and
logic to apply a second control voltage to turn off the second subset o

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting
• Chang Kuo-Pin

Classifications

• G11C2216/18

  Flash erasure of all the cells in an array, sector or block simultaneously · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• H01L27/11551

  Electricity · mapped topic