Method of initializing 3D non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9685235-B2
Application number	US-201615351349-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Nov 14, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.

First claim

What is claimed is:

1. A method of initializing a three-dimensional (3D) non-volatile memory device, the 3D non-volatile memory device comprising a dummy string selection line, a plurality of string selection lines, a plurality of wordlines, a plurality of bitlines, a ground selection line, and a plurality of memory layers, each of the memory layers comprising a plurality of channel lines respectively coupled to the plurality of bitlines via first ends of the plurality of channel lines and coupled to a common source line of the memory layer via second ends of the plurality of channel lines, wherein the dummy string selection line, the plurality of string selection lines, the plurality of wordlines, and the ground selection line intersect with the plurality of channel lines, and each of the plurality of channel lines defines a memory string, the method comprising:
programming a plurality of string selection transistors coupled with the plurality of string selection lines to have at least one or more threshold values; and
programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the plurality of string selection transistors function as string selection transistors.

2. The method of claim 1 , wherein programming a plurality of string selection transistors comprises:
applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers, the selected string selection line being coupled to a plurality of string selection transistors;
verifying whether threshold voltages of the plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors;
programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines, the predetermined threshold voltage being suitable to make each of the programmed memory cell transistors function as a screening transistor; and
program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selection transistors.

3. The method of claim 2 , wherein applying the first program voltage, verifying whether the threshold voltages of the plurality of string selection transistors reach the target value, and applying the third program voltage respectively include performing an incremental step pulse programming (ISPP) technique.

4. The method of claim 2 , wherein verifying whether the threshold voltages of the plurality of string selection transistors reach the target value includes:
applying a sensing voltage to the plurality of bitlines; and
applying a voltage substantially equal to the sensing voltage to common source lines of unselected memory layers among the plurality of memory layers.

5. The method of claim 2 , wherein programming the memory cell transistors of the one or more of memory strings coupled with the programmed string selection transistors includes program-inhibiting a memory cell transistor of a memory string coupled with a corresponding one of the unprogrammed string selection transistors.

6. The method of claim 5 , wherein programming the memory cell transistors further includes applying a voltage equal to or higher than a common collector voltage to a bitline coupled with the corresponding one of the unprogrammed string selection transistors to induce channel potential boosting at the memory string coupled with the corresponding unprogrammed string selection transistor.

7. The method of claim 2 , wherein program-inhibiting channel lines of the programmed string selection transistors includes:
applying a ground voltage to a common source line of the selected memory layer; and
applying a common collector voltage to common source lines of unselected memory layers among the plurality of memory layers and to the plurality of bitlines to float channel lines of memory strings of the unselected memory layers.

8. The method of claim 2 , wherein program-inhibiting the channel lines of the programmed string selection transistors includes:
applying a voltage smaller than the threshold voltages of the programmed memory cell transistors to the selected wordline coupled with the programmed memory cell transistors; and
applying the third program voltage to the selected string selection line to selectively program the unprogrammed string selection transistors.

9. The method of claim 1 , wherein programming a plurality of string selection transistors is performed by using the dummy string selection line.

10. The method of claim 1 , further comprising: before applying the first program voltage to a selected string selection line, erasing the plurality of string selection transistors coupled with the plurality of string selection lines and a plurality of memory cell transistors coupled with the plurality of wordlines.

11. The method of claim 1 , wherein programming a dummy string selection transistor includes:
initially levelling the dummy string selection transistor by programming threshold values of the dummy string selection transistor to have a determined first target value; and
programming the initially levelled dummy string selection transistor to have a second target value by applying an erase voltage signal to the common source line of the selected memory layer, such that the programmed dummy string selection transistor functions as string selection transistors.

12. The method of claim 11 , wherein the erase voltage signal has a level selected based on the second target value.

13. The method of claim 11 , wherein the erase voltage signal is an erase voltage signal having a time varying section, and the dummy string selection transistors are programmed to the second target value by grounding or floating the dummy string selection line in the time varying section of the erase voltage signal.

14. The method of claim 11 , wherein the time varying section of the time varying erase voltage signal comprises a ramping section, a step-like section, or a combination thereof.

15. The method of claim 11 , wherein the time varying section comprises an increasing ramp section or a decreasing ramp section.

16. The method of claim 11 , wherein the time varying erase voltage signal is applied to a first common source line coupled to the selected first memory layer, the method further comprising:
applying a voltage signal for erase inhibition to one or more of common source lines other than the first common source line, the one or more common source lines being coupled to one or more of unselected memory layers among the plurality of memory layers when the time varying erase voltage signal is applied and the threshold values of the first plurality of string selection transistors in the first memory layer are set.

17. The method of claim 11 , further comprising causing the plurality of bitlines to float when the first time varying erase voltage signal is applied.

18. The method of claim 1 , wherein the plurality of channel lines of the 3D non-volatile memory device have a channel stacked structure, a straig

Assignees

• Sk Hynix Inc
• Univ Seoul Nat R & Db Found

Inventors

• Park Byung Gook
• Kwon Dae Woong
• Kim Do Bin
• Lee Sang Ho

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title