3D multi-layer non-volatile memory device with planar string and method of programming

Patent metadata

Field	Value
Publication number	US-9859010-B2
Application number	US-201514703196-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	Nov 25, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers includes one or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in series between a plurality of bit lines and a common source line, and the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected.

First claim

What is claimed is:

1. A semiconductor memory device, comprising a plurality of memory layers stacked on a semiconductor substrate,
wherein each of the plurality of memory layers comprises a plurality of cell strings electrically coupled between a plurality of bit lines and a common source line and each of the plurality of cell strings comprises two or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in sequence between each of the plurality of bit lines and the common source line, and
the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected,
wherein the connection control transistors are different from the drain select transistors,
wherein the connection control transistor is erased by an erase voltage applied through the common source line or erased by boosting a channel to a designated potential, and
wherein the two or more connection control transistors are programmed before a program operation on the one or more drain select transistors of a selected memory layer among the plurality of memory layers is performed.

2. The semiconductor memory device of claim 1 , wherein a non-selected memory layer and the plurality of bit lines are electrically disconnected in the program operation of the selected memory layer.

3. The semiconductor memory device of claim 2 , wherein, in the program operation, the connection control transistors are turned on by a program-allowing voltage applied to a selected bit line among the plurality of bit lines, and are turned off by a program-inhibiting voltage applied to a non-selected bit line.

4. A method of operating a semiconductor memory device comprising a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers comprises a plurality of cell strings electrically coupled between a plurality of bit lines and a common source line and each of the plurality of cell strings comprises first and second connection control transistors, a drain select transistor, a plurality of memory cells, and a source select transistor electrically coupled in sequence between each of the plurality of bit lines and the common source line, the method comprising:
programming the first and second connection control transistors of the plurality of memory layers;
erasing the second connection control transistor adjacent to the drain select transistor of a selected memory layer;
coding-programming the drain select transistor of the selected memory layer;
programming the second connection control transistor of the selected memory layer; and
erasing the first and second connection control transistors,
wherein the connection control transistors are different from the drain select transistors.

5. The method of operating the semiconductor memory device of claim 4 , after the programming of the second connection control transistor, performing again from the erasing of the second connection control transistor of the selected memory layer by selecting a next memory layer when the selected memory layer is not a last memory layer among the plurality of memory layers.

6. The method of operating the semiconductor memory device of claim 4 , wherein the erasing of the second connection control transistor of the selected memory layer selectively erases only the programmed second connection control transistor by applying an erase voltage to the common source line to which the selected memory layer is electrically coupled.

7. The method of operating the semiconductor memory device of claim 4 , wherein the erasing of the second connection control transistor of the selected memory layer selectively erases only the programmed second connection control transistor by applying a pass voltage to the drain select transistor and the plurality of memory cells and boosting a channel of the selected memory layer after applying a power supply voltage to the common source line of the selected memory layer.

8. The method of operating the semiconductor memory device of claim 4 , wherein the coding-programming of the drain select transistor of the selected memory layer turns on the second connection control transistor electrically coupled to a selected bit line among the second connection control transistors of the selected memory layer, and turns off the second connection control transistor electrically coupled to a non-selected bit line by applying a program-allowing voltage to the selected bit line among the plurality of bit lines and applying a program-inhibiting voltage to the non-selected bit line.

9. The method of operating the semiconductor memory device of claim 4 , wherein the common source lines electrically coupled to each of the plurality memory layers are electrically disconnected.

10. A method of operating a semiconductor memory device comprising a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers comprises a plurality of cell strings electrically coupled between a plurality of bit lines and a common source line and each of the plurality of cell strings comprises first and second connection control transistors, a drain select transistor, a plurality of memory cells, and a source select transistor electrically coupled in sequence between each of the plurality of bit lines and the common source line, the method comprising:
programming the second connection control transistor adjacent to the drain select transistor of the plurality of memory layers;
erasing the second connection control transistor of a selected memory layer;
coding-programming the drain select transistor of the selected memory layer;
programming the second connection control transistor of the selected memory layer; and
erasing the first and second connection control transistors of the plurality of memory layers,
wherein the connection control transistors are different from the drain select transistors.

11. The method of operating the semiconductor memory device of claim 10 , after the programming of the second connection control transistor, performing again from the erasing of the second connection control transistor of the selected memory layer by selecting a next memory layer when the selected memory layer is not a last memory layer among the plurality of memory layers.

12. The method of operating the semiconductor memory device of claim 10 , wherein the erasing of the second connection control transistor of the selected memory layer selectively erases only the programmed second connection control transistor by applying an erase voltage to the common source line to which the selected memory layer is electrically coupled.

13. The method of operating the semiconductor memory device of claim 10 , wherein the erasing of the second connection control transistor of the selected memory layer selectively erases only the second connection control transistor programmed by applying a pass voltage to the drain select transistor and the plurality of memory cells and boosting a channel of the selected memory layer after applying a power supply voltage to the common source line of the selected memory layer.

14. The method of operating the semiconductor memory device of claim 10 , wherein the coding-programming of the drain select transistor of the selected memory layer turns on the second connection control transistor electrically coupled to a selected bit line among the second connection control transistors of the selected memory layer, and turns off t

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title