Nonvolatile memory devices, operating methods thereof and memory systems including the same

Patent metadata

Field	Value
Publication number	US-9747995-B2
Application number	US-201615176269-A
Country	US
Kind code	B2
Filing date	Jun 8, 2016
Priority date	Feb 17, 2010
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

First claim

What is claimed is:

1. A method of programming a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
programming each of the plurality of serially-connected nonvolatile memory cells by an incremental step pulse program (ISPP) method that uses a program voltage including an initial program voltage and an increment, a level of the program voltage increasing by the increment from a level of the initial program voltage; and
verifying each of the plurality of serially-connected nonvolatile memory cells,
wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate,
the level of the initial program voltage of the program voltage that is applied to a corresponding one of the plurality of serially-connected nonvolatile memory cells is related with a distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate,
the level of the initial program voltage of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cells is higher as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater in a first portion of the first memory cell string, and
the level of the initial program voltage of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cell is lower as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate become greater in a second portion.

2. The method of claim 1 , wherein the level of the initial program voltage of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cells is higher as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater in a third portion of the first memory cell string.

3. The method of claim 1 , wherein the increment of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cells is related with the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate.

4. The method of claim 3 , wherein the level of the increment of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cell is lower as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater in the first portion of the first memory cell string.

5. The method of claim 3 , wherein the level of the increment of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cell is lower as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate become greater in the second portion.

6. The method of claim 3 , wherein the level of the increment of the program voltage that is applied to the corresponding one of the plurality of serially-connected nonvolatile memory cells is higher as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater in a third portion of the first memory cell string.

7. The method of claim 1 , wherein the plurality of serially-connected nonvolatile memory cells are divided into a plurality of groups,
each of the plurality of groups includes a first nonvolatile memory cell and a second nonvolatile memory cell, the first nonvolatile memory cell and the second nonvolatile memory cell being included in the plurality of serially-connected nonvolatile memory cells, and
the level of the initial program voltage of the program voltage applied to the first nonvolatile memory cell is equal to the level of the initial program voltage of the program voltage applied to the second nonvolatile memory cell.

8. The method of claim 7 , wherein the plurality of groups include a first group and a second group that both belong to one of the first portion and the second portion,
a distance between the first group and the substrate is greater than a distance between the second group and the substrate, and
the level of the initial program voltage of the program voltage applied to a third nonvolatile memory cell of the first group is higher than the level of the initial program voltage of the program voltage applied to a fourth nonvolatile memory cell of the second group.

9. The method of claim 8 , wherein the increment of the program voltage applied to the first nonvolatile memory cell is equal to the increment of the program voltage applied to the second nonvolatile memory cell, and
the increment of the program voltage applied to the third nonvolatile memory of the first group is greater than the increment of the program voltage applied to the fourth nonvolatile memory of the second group.

10. The method of claim 1 , wherein the plurality of memory cell strings are divided into a first group connected to a first bit-line and a second group connected to a second bit-line,
the first memory cell string among the first group and a second memory string among the second group are connected to a first string selection line (SSL), and
a third memory cell string among the first group and a fourth memory string among the second group are connected to a second SSL.

11. The method of claim 1 , wherein the first memory cell string has a ground select transistor (GST) directly connected to a source line, and
a distance between the GST and the substrate is greater than a distance between at least one of the plurality of serially-connected nonvolatile memory cells of the first memory cell string and the substrate.

12. The method of claim 1 , wherein a distance between the second portion and the substrate is greater than a distance between the first portion and the substrate.

13. A method of programming a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
programming a first memory cell among the plurality of serially-connected nonvolatile memory cells by an incremental step pulse program (ISPP) method that uses a first program voltage, the first program voltage having a first initial program voltage and a first increment, a level of the first program voltage increasing by the first increment from a level of the first initial program voltage;
programming a second memory cell among the plurality of serially-connected nonvolatile memory cells by the ISPP method that uses a second program voltage, the second program voltage including a second initial program voltage and a second increment, a level of the second program voltage increasing by the second increment from a level of the second initial program voltage, the level of the second initial program voltage being higher than the level of the first initial program voltage,
programming a third memory cell among the plurality of serially-connected nonvolatile memory cells by the ISPP method that uses a third program voltage, the third program v

Assignees

• Shim Sun-Il
• Jang Jae-Hoon
• Chae Donghyuk
• Lim Youngho
• Kim Hansoo
• Jeong Jaehun
• Samsung Electronics Co Ltd

Inventors

• Shim Sun-Il
• Jang Jae-Hoon
• Chae Donghyuk
• Lim Youngho
• Kim Hansoo
• Jeong Jaehun

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title