Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same

Patent metadata

Field	Value
Publication number	US-10600487-B2
Application number	US-201816205334-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Mar 12, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

First claim

What is claimed is:

1. A method of erasing data in a nonvolatile memory device, comprising:
applying an erase voltage to an erase source terminal of a memory block having a plurality of memory cells therein, which are stacked in a vertical direction relative to an underlying substrate;
applying a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the memory block as an erase target block; and
applying a second voltage to a second selection line among the plurality of selection lines, the second voltage being lower than the erase voltage, the second selection line being disposed farther from the erase source terminal than the first selection line and being used for selecting the memory block as the erase target block.

2. The method of claim 1 , wherein:
the first voltage starts to apply to the first selection line at a first time point, and
the erase voltage starts to apply to the erase source terminal at a second time point later than the first time point.

3. The method of claim 2 , wherein the second voltage starts to apply to the second selection line at a third time point later than the second time point.

4. The method of claim 1 , wherein applying the erase voltage to the erase source terminal includes:
applying the erase voltage to a common source line contact that is disposed in a lower portion of the memory block.

5. The method of claim 4 , wherein applying the first voltage to the first selection line includes:
applying the first voltage to a first ground selection line that is a lowermost ground selection line among at least two ground selection lines in the memory block.

6. The method of claim 5 , wherein applying the second voltage to the second selection line includes:
applying the second voltage to a second ground selection line that is disposed upper than the first ground selection line.

7. The method of claim 1 , wherein applying the erase voltage to the erase source terminal includes:
applying the erase voltage to a bitline that is disposed in an upper portion of the memory block.

8. The method of claim 7 , wherein applying the first voltage to the first selection line includes:
applying the first voltage to a first string selection line that is an uppermost string selection line among at least two string selection lines in the memory block.

9. The method of claim 8 , wherein applying the second voltage to the second selection line includes:
applying the second voltage to a second string selection line that is disposed lower than the first string selection line.

10. The method of claim 1 , further comprising:
determining whether a first number representing a number of times in which a data erase operation has been performed is greater than a reference number; and
changing a data erase scheme to perform the data erase operation when the first number is greater than the reference number.

11. The method of claim 10 , wherein changing the data erase scheme to perform the data erase operation includes:
applying the erase voltage to the erase source terminal;
applying the first voltage to the first selection line and the second selection line; and
applying the second voltage to a third selection line among the plurality of selection lines, the third selection line being disposed farther from the erase source terminal than the second selection line and being used for selecting the memory block as the erase target block.

12. The method of claim 10 , further comprising:
maintaining the data erase scheme to perform the data erase operation when the first number is smaller than or equal to the reference number.

13. The method of claim 1 , wherein the nonvolatile memory device has a cell over periphery (COP) structure in which a peripheral circuit is formed on a semiconductor substrate and a memory cell array including the memory block is stacked on the peripheral circuit.

14. A method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells being disposed in a vertical direction in each memory block, each memory block being divided into a first sub-block and a second sub-block in the vertical direction, the method comprising:
applying an erase voltage to an erase source terminal of a memory block;
applying a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the first sub-block as an erase target sub-block; and
applying the first voltage or a second voltage to a second selection line among the plurality of selection lines based on a location relationship between the erase source terminal and the first sub-block, the second voltage being lower than the erase voltage, the second selection line being disposed farther from the erase source terminal than the first selection line and being used for selecting the first sub-block as the erase target sub-block.

15. The method of claim 14 , wherein:
when the first sub-block is disposed upper than the second sub-block and the erase voltage is provided to the first sub-block from a common source line contact that is disposed in a lower portion of the memory block,
applying the erase voltage to the erase source terminal includes applying the erase voltage to the common source line contact,
applying the first voltage to the first selection line includes applying the first voltage to a first ground selection line that is a lowermost ground selection line among at least two ground selection lines in the memory block, and
applying the first voltage or the second voltage to the second selection line includes applying the first voltage to a second ground selection line that is disposed upper than the first ground selection line.

16. The method of claim 15 , further comprising:
applying the first voltage to wordlines connected to the second sub-block and a first dummy wordline disposed between the first sub-block and the second sub-block; and
applying the second voltage to a second dummy wordline disposed upper than the first dummy wordline and between the first sub-block and the second sub-block.

17. The method of claim 14 , wherein:
when the first sub-block is disposed upper than the second sub-block and the erase voltage is provided to the first sub-block from a bitline that is disposed in an upper portion of the memory block,
applying the erase voltage to the erase source terminal includes applying the erase voltage to the bitline,
applying the first voltage to the first selection line includes applying the first voltage to a first string selection line that is an uppermost string selection line among at least two string selection lines in the memory block, and
applying the first voltage or the second voltage to the second selection line includes applying the second voltage to a second string selection line that is disposed lower than the first string selection line.

18. A method of erasing data in a memory block within the nonvolatile memory device, comprising:
applying a non-zero erase voltage to a source terminal of a first ground selection transistor within a vertical NAND string of memory cells comprising at least two ground sele

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Kwak Dong-Hun
• Yoon Chi-Weon

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/24

  Bit-line control circuits · CPC title