Semiconductor device

Patent metadata

Field	Value
Publication number	US-9330771-B2
Application number	US-201514619953-A
Country	US
Kind code	B2
Filing date	Feb 11, 2015
Priority date	Oct 1, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings.

First claim

What is claimed is:

1. A semiconductor device, comprising:
memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively; and
an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings,
wherein the operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings.

2. The semiconductor device of claim 1 ,
wherein the operation circuit performs a pre-program operation on the drain select transistors included in the memory strings before the erase operations on the drain select transistors are performed.

3. The semiconductor device of claim 2 ,
wherein the operation circuit continuously applies pre-program pulses, having voltage levels that gradually increase, to the drain select line at predetermined times to perform the pre-program on the drain select transistors.

4. The semiconductor device of claim 1 ,
wherein the operation circuit performs an erase operation on a drain select transistor included in a memory string selected first among the memory strings when the erase operations are performed on the memory cells included in the memory strings.

5. The semiconductor device of claim 1 ,
wherein the operation circuit performs an erase verify operation on a drain select transistor included in a selected memory string among the memory strings after performing an erase operation on the drain select transistor included in the selected memory string and before performing an erase operation on a drain select transistor included in a subsequent memory string.

6. The semiconductor device of claim 1 ,
wherein the operation circuit performs a post-program operation on a drain select transistor included in a selected memory string after performing an erase operation on the drain select transistor included in the selected memory string and before performing an erase operation on a drain select transistor included in a subsequent memory string.

7. The semiconductor device of claim 6 ,
wherein the operation circuit performs a verify operation whenever the post-program operation is performed while increasing program voltages applied to the drain select transistor.

8. The semiconductor device of claim 6 ,
wherein the operation circuit alternately performs the post-program operation and a post-program verify operation after performing the post-program operation a predetermined number of times while increasing program voltages applied to the drain select transistor.

9. The semiconductor device of claim 1 ,
wherein the operation circuit performs an erase operation on a drain select transistor included in a first memory string among the memory strings when an erase operation is performed on the memory cells included in the memory strings.

10. The semiconductor device of claim 9 ,
wherein the operation circuit performs a post-program operation and a post-program verify operation on the drain select transistor included in the first memory string after performing the erase operation on the drain select transistor included in the first memory string.

11. The semiconductor device of claim 10 ,
wherein the operation circuit performs a post-program operation and a post-program verify operation on a drain select transistor included in a subsequent memory string among the memory strings after completing the post-program operation and the post-program verify operation on the drain select transistor included in the first memory string.

12. The semiconductor device of claim 10 ,
wherein the operation circuit simultaneously performs a post-program operation and a post-program verify operation on drain select transistors included in the remaining memory strings after completing the post-program operation and the verify operation on the drain select transistor included in the first memory string.

13. A semiconductor device, comprising:
memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively; and
an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings,
wherein the operation circuit performs an erase operation on the drain select transistor included in a first memory string among the memory strings when an erase operation is performed on the memory cells included in the memory strings.

14. The semiconductor device of claim 13 ,
wherein the operation circuit performs a pre-program operation on drain select transistors included in the memory strings before the erase operation on the drain select transistor included in the first memory string is performed.

15. The semiconductor device of claim 14 ,
wherein the operation circuit continuously applies pre-program pulses of which voltage levels gradually increase to the drain select line a predetermined number of times to perform the pre-program operation on the drain select transistors.

16. The semiconductor device of claim 15 ,
wherein the operation circuit performs a pre-program verify operation on the drain select transistors after applying the respective pre-program pulses.

17. The semiconductor device of claim 13 ,
wherein the operation circuit performs an erase verify operation after performing the erase operation on the drain select transistor included in the first memory string.

18. The semiconductor device of claim 15 ,
wherein the operation circuit performs a post-program operation on the drain select transistor included in the first memory string after performing the erase operation on the drain select transistor included in the first memory string.

19. The semiconductor device of claim 18 ,
wherein the operation circuit performs a post-program verify operation after performing the post-program operation on the drain select transistor included in the first memory string.

20. The semiconductor device of claim 18 ,
wherein the operation circuit performs a post-program operation on drain select transistors included in the remaining memory strings after performing the post-program operation on the drain select transistor included in the first memory string.

Assignees

• Sk Hynix Inc

Inventors

• Shim Jung Woon

Classifications

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title