3-dimensional semiconductor device having memory cells stacked over substrate

Patent metadata

Field	Value
Publication number	US-9299447-B2
Application number	US-201414490484-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Mar 25, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of memory blocks, wherein each of the plurality of memory blocks comprises:
a first select transistor electrically coupled to a common source line;
a second select transistor electrically coupled to a bit line;
a plurality of memory cells electrically coupled between the first and second select transistors; and
an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, applying a first positive voltage to gates of the first select transistors of unselected memory blocks of the plurality of memory blocks, and setting word lines coupled to gates of the memory cells of the unselected memory blocks to a floating state when an erase voltage is applied to the common source line during the erase operation.

2. The semiconductor device of claim 1 , wherein the operation circuit is suitable for adjusting a difference between the erase voltage and the first positive voltage to reduce a gate induced drain leakage (GIDL) phenomenon in the first select transistor.

3. The semiconductor device of claim 1 , wherein the operation circuit is suitable for adjusting a difference between the erase voltage and the first positive voltage, wherein the first select transistor transfers a voltage that is relatively lower than the first positive voltage to the plurality of memory cells.

4. The semiconductor device of claim 1 , wherein each of the plurality of memory cells comprises:
a first dummy memory cell electrically coupled to the first select transistor;
a second dummy memory cell electrically coupled to the second select transistor; and
main memory cells electrically coupled between the first and second dummy memory cells.

5. The semiconductor device of claim 4 , wherein the operation circuit is suitable for applying a second positive voltage to a gate of the first dummy memory cell of each of the unselected memory blocks during the erase operation.

6. The semiconductor device of claim 5 , wherein the second positive voltage is relatively lower than the first positive voltage.

7. The semiconductor device of claim 5 , wherein the operation circuit is suitable for adjusting a difference between the voltage transferred by the first select transistor and the second positive voltage, wherein a voltage that is relatively lower than the second positive voltage is transferred by the first dummy memory cell with a reduction in a gate induced drain leakage (GIDL) in the first dummy memory cell.

8. The semiconductor device of claim 5 , wherein gates of the main memory cells, the second dummy memory cell and the second select transistor in the unselected memory blocks are set to a floating state.

9. The semiconductor device of claim 1 , wherein the operation circuit comprises:
a first voltage generation circuit suitable for transmitting the operation voltages to global lines and transmitting the erase voltage to the common source line during the erase operation;
a switching circuit configured to electrically couple first and second select lines and word lines of the selected memory block to the global lines in response to block select signals; and
a second voltage generation circuit suitable for applying the first positive voltage to first select lines of the first select transistors in the unselected memory blocks during the erase operation.

10. The semiconductor device of claim 9 , wherein the second voltage generation circuit is suitable for applying the first positive voltage to the first select lines of the first select transistors in response to inverted block select signals.

11. The semiconductor device of claim 1 , wherein the word lines comprise:
a first dummy word line coupled to a gate of a first dummy memory cell which is electrically coupled to the first select transistor;
a second dummy word line coupled to a gate of a second dummy memory cell which is electrically coupled to the second select transistor; and
main word lines of main memory cells disposed between the first and second dummy word lines.

12. The semiconductor device of claim 11 , wherein the operation circuit is suitable for applying a second positive voltage to the first dummy word line of the first dummy memory cell in each of the unselected memory blocks during the erase operation.

13. The semiconductor device of claim 12 , wherein the second positive voltage is relatively lower than the first positive voltage.

14. The semiconductor device of claim 12 , wherein the operation circuit is suitable for adjusting a difference between a voltage transferred by the first select transistor and the second positive voltage so that a relatively lower voltage than the second positive voltage is transferred by the first dummy memory cells and a GIDL phenomenon in the first dummy memory cell is reduced.

15. The semiconductor device of claim 11 , wherein the second dummy word lines, and the second select lines in the unselected memory blocks are set to a floating state.

16. The semiconductor device of claim 1 , wherein each of the memory blocks further comprises a pipe transistor formed on a semiconductor substrate,
the first select transistor and a first subset of the plurality of the memory cells are electrically coupled in series between the common source line and the pipe transistor, and
the second select transistor and a second subset of the plurality of memory cells are electrically coupled in series between the bit line and the pipe transistor.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun
• Heo Hyun
• Koo Min Gyu
• Lee Dong Hwan

Classifications

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title