Method of initializing and driving 3D non-volatile memory device using time varying erase signal

Patent metadata

Field	Value
Publication number	US-9754673-B2
Application number	US-201615342039-A
Country	US
Kind code	B2
Filing date	Nov 2, 2016
Priority date	Nov 3, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.

First claim

What is claimed is:

1. A method of initializing a three-dimensional (3D) non-volatile memory device, the 3D non-volatile memory device comprising a plurality of string selection lines, a plurality of wordlines, a ground selection line, and a plurality of memory layers, each of the memory layers comprising a plurality of channel lines respectively coupled to a plurality of bitlines via first ends of the plurality of channel lines and coupled to a common source line via second ends of the plurality of channel lines, wherein the plurality of string selection lines, the plurality of wordlines, and the ground selection line intersect with the plurality of channel lines, and each of the plurality of channel lines defines a memory string and the memory string has string selection transistors respectively coupled with the plurality of string selection lines, the method comprising:
initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level;
applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers, the initially leveled string selection transistors including a first plurality of string selection transistors in the first memory layer; and
setting threshold voltages of the first plurality of string selection transistors in the first memory layer by controlling each of the plurality of string selection lines coupled with the first plurality of string selection transistors during a first time interval corresponding to the first time varying section of the first time varying erase voltage signal.

2. The method of claim 1 , further comprising:
selecting a second memory layer among the plurality of memory layers comprising the initially leveled string selection transistors, and applying a second time varying erase voltage signal having a second time varying section to a second plurality of channel lines of the second selected memory layer; and
setting respective threshold voltages of a second plurality of string selection transistors in the second memory layer by controlling the plurality of string selection lines respectively coupled with corresponding ones of the second plurality of string selection transistors during a second time interval corresponding to the second time varying section of the second time varying erase voltage signal.

3. The method of claim 1 , wherein the predetermined target level includes a plurality of target levels respectively corresponding to the plurality of memory layers, the plurality of target levels being different from one another.

4. The method of claim 1 , wherein the first time varying section of the first time varying erase voltage signal is a single time varying section.

5. The method of claim 1 , wherein the first time varying section of the first time varying erase voltage signal comprises a ramping section, a step-like section, or a combination thereof.

6. The method of claim 1 , wherein the first time varying section comprises an increasing ramp section or a decreasing ramp section.

7. The method of claim 1 , wherein the first time varying erase voltage signal is applied to a first common source line coupled to the selected first memory layer, the method further comprising:
applying a voltage signal for erase inhibition to one or more of common source lines other than the first common source line, the one or more common source lines being coupled to one or more of unselected memory layers among the plurality of memory layers when the first time varying erase voltage signal is applied and the threshold voltages of the first plurality of string selection transistors in the first memory layer are set.

8. The method of claim 7 , wherein the voltage signal for erase inhibition has a positive voltage level that is smaller than a maximum level of the first time varying erase voltage signal.

9. The method of claim 1 , further comprising causing the plurality of bitlines to float when the first time varying erase voltage signal is applied and the threshold voltages of the first plurality of string selection transistors in the first memory layer are set.

10. The method of claim 1 , further comprising causing the plurality of wordlines to float when the first time varying erase voltage signal is applied and the threshold voltages of the first plurality of string selection transistors in the first memory layer are set.

11. The method of claim 1 , wherein, when the first time varying section of the first time varying erase voltage signal has an increasing ramp section, controlling each of the plurality of string selection lines includes causing each of the string selection lines that were in a ground state to float at a plurality of time points within the first time interval corresponding to the first time varying section to terminate erase operations for the first plurality of string selection transistors at the plurality of time points, respectively.

12. The method of claim 1 , wherein, when the first time varying section of the time varying erase voltage signal has a decreasing ramp section, controlling each of the plurality of string selection lines includes grounding each of the plurality of string selection lines that were in a floated state at a plurality of time points within the first time interval corresponding to the first time varying section to start erase operations for the first plurality of string selection transistors at the plurality of time points, respectively.

13. The method of claim 1 , wherein the channel lines of the 3D non-volatile memory device have a channel stacked structure, a straight-shaped bit cost scalable (BiCs) structure, a pipe-shaped BiCs structure, or a combination thereof.

14. The method of claim 1 , wherein the 3D non-volatile memory device is a NAND flash memory device.

15. A method of driving a 3D non-volatile memory device, the 3D non-volatile memory device comprising a plurality of string selection lines, a plurality of wordlines, a ground selection line, and a plurality of memory layers, each of the memory layers comprising a plurality of channel lines respectively coupled to bitlines via first ends of the plurality of channel lines and coupled to a common source line via second ends of the plurality of channel lines, wherein the plurality of string selection lines, the plurality of wordlines, and the ground selection line intersect with the plurality of channel lines, and each of the plurality of channel lines defines a memory string and the memory string has string selection transistors respectively coupled with the plurality of string selection lines, the method comprising:
initially leveling threshold voltages of string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level;
applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer, the first memory layer being one of the plurality of memory layers, the initially leveled string selection transistors including a first plurality of string selection transistors in the first memory layer;
setting threshold voltages of the first plurality of string selection transistors in the first memory layer by controlling each of the plurality of string selection lines coupled with the first plurality of string selection transistors during a first time interval corresponding to the first time varying section of the first time varying erase

Assignees

• Sk Hynix Inc
• Univ Seoul Nat R & Db Found

Inventors

• Park Byung Gook
• Kwon Dae Woong
• Kim Do Bin
• Lee Sang Ho

Classifications

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title