Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance

Patent metadata

Field	Value
Publication number	US-10840335-B2
Application number	US-201816193000-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 16, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween;
forming a gate on the channel region;
forming a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region;
the body contact dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a metal contact on the second body contact region.

2. The method of claim 1 wherein the source and drain regions and the body contact are on a top side of the semiconductor layer.

3. The method of claim 1 wherein the source and drain regions are on a top side of the semiconductor layer, and the body contact is on a back side of the semiconductor layer opposite the top side.

4. The method of claim 1 wherein the second body contact region is level with a top side of the semiconductor layer.

5. The method of claim 1 wherein the second body contact region is raised above a top side of the semiconductor layer.

6. The method of claim 1 wherein the first body contact region comprises a different material than the second body contact region.

7. The method of claim 6 wherein the first body contact region comprises silicon; and wherein the second body contact region comprises silicon germanium.

8. The method of claim 6 wherein the first body contact region comprises silicon germanium; and wherein the second body contact region comprises silicon.

9. The method of claim 1 wherein the metal contact comprises at least one of titanium, cobalt, nickel and platinum.

10. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

11. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

12. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween;
forming a gate on the channel region;
forming a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region;
the body contact dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, the at least one oxygen monolayer being constrained within a crystal lattice of adjacent base silicon portions; and
forming a metal contact on the second body contact region;
wherein the second body contact region is level with a top side of the semiconductor layer.

13. The method of claim 12 wherein the source and drain regions and the body contact are on the top side of the semiconductor layer.

14. The method of claim 12 wherein the source and drain regions are on the top side of the semiconductor layer, and the body contact is on a back side of the semiconductor layer opposite the top side.

15. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween;
forming a gate on the channel region;
forming a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region;
the body contact dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, the at least one oxygen monolayer being constrained within a crystal lattice of adjacent base silicon portions; and
forming a metal contact on the second body contact region;
wherein the second body contact region is raised above a top side of the semiconductor layer.

16. The method of claim 15 wherein the source and drain regions and the body contact are on the top side of the semiconductor layer.

17. The method of claim 15 wherein the source and drain regions are on the top side of the semiconductor layer, and the body contact is on a back side of the semiconductor layer opposite the top side.

18. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween;
forming a gate on the channel region;
forming a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and a second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region, and with the first body contact region comprising a different material than the second body contact region;
the body contact dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions.

19. The method of claim 18 wherein the source and drain regions and the body contact are on a top side of the semiconductor layer.

20. The method of claim 18 wherein the source and drain regions are on a top side of the semiconductor layer, and the body contact is on a back side of the semiconductor layer opposite the top side.

21. The method of claim 18 wherein the first body contact region comprises silicon; and wherein the second body contact region comprises silicon germanium.

22. The method of claim 18 wherein the first body contact region comprises silicon germanium; and wherein the second body contact region comprises silicon.

23. The method of claim 18 wherein the base semiconductor monolayers comprise silicon, and the at least one non-semiconductor monolayer comprises oxygen.

Assignees

• Atomera Inc

Inventors

• Takeuchi Hideki
• Connelly Daniel
• Hytha Marek
• Burton Richard
• Mears Robert J

Classifications

• H10D62/8162

  having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation · CPC title

• H10D62/822 Primary

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/027

  of lateral single-gate IGFETs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title