Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-2026047165-A1 · Feb 12, 2026 · US
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Hytha Marek patents
Hytha Marek is listed as an inventor on 107 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hytha Marek |
| Total patents | 107 |
| First publication | Feb 8, 2018 |
| Latest publication | Feb 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Methods for making surface acoustic wave (saw) devices including a superlattice
US-2025373219-A1 · Dec 4, 2025 · US
Surface acoustic wave (saw) devices including a superlattice and related methods
US-2025373225-A1 · Dec 4, 2025 · US
Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-12477798-B2 · Nov 18, 2025 · US
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-2025273460-A1 · Aug 28, 2025 · US
Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
US-2025259841-A1 · Aug 14, 2025 · US
Method for making semiconductor device including superlattice source/drain
US-2025248090-A1 · Jul 31, 2025 · US
Semiconductor device including superlattice source/drain
US-2025248091-A1 · Jul 31, 2025 · US
Method for making semiconductor devices with group iii-n and silicon device regions above a superlattice layer
US-2025239448-A1 · Jul 24, 2025 · US
Semiconductor devices with group iii-n and silicon device regions above a superlattice layer and related methods
US-2025241034-A1 · Jul 24, 2025 · US
Recent patents
Latest publications not already listed above.
Method for making semiconductor devices including compound semiconductor materials with a superlattice layer
US-2025241018-A1 · Jul 24, 2025 · US
Semiconductor devices including compound semiconductor materials with a superlattice layer
US-2025241035-A1 · Jul 24, 2025 · US
Method for making semiconductor devices including compound semiconductor materials using a superlattice separation layer
US-2025239447-A1 · Jul 24, 2025 · US
Piezoelectric devices including compound semiconductor materials and a superlattice layer
US-2025241033-A1 · Jul 24, 2025 · US
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-12322594-B2 · Jun 3, 2025 · US
Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
US-12315723-B2 · May 27, 2025 · US
Method of fabricating semiconductor devices with isolated superlattice structures
US-2025125149-A1 · Apr 17, 2025 · US
Method for making a semiconductor device using superlattices with different non-semiconductor thermal stabilities
US-2025105021-A1 · Mar 27, 2025 · US
Semiconductor device including superlattice with o18 enriched monolayers
US-2025107192-A1 · Mar 27, 2025 · US
Method for making complementary field effect transistor (cfet) devices including superlattice isolation layer
US-2025048718-A1 · Feb 6, 2025 · US
Method for making gate-all-around (gaa) device including a superlattice
US-2025048701-A1 · Feb 6, 2025 · US
Complementary field effect transistor (cfet) devices including superlattice isolation layer
US-2025048729-A1 · Feb 6, 2025 · US
Semiconductor device including superlattice with O18 enriched monolayers
US-12199148-B2 · Jan 14, 2025 · US
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities
US-12191160-B2 · Jan 7, 2025 · US
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US-2025006794-A1 · Jan 2, 2025 · US
Method for making gate-all-around (GAA) device including a superlattice
US-12142641-B2 · Nov 12, 2024 · US
Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US-12119380-B2 · Oct 15, 2024 · US
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-2024339319-A1 · Oct 10, 2024 · US
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US-12046470-B2 · Jul 23, 2024 · US
Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
US-2024194482-A1 · Jun 13, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Atomera Inc | 107 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D62/8162 | 101 |
| H10D30/751 | 60 |
| H10P14/3252 | 55 |
| H10P14/3211 | 44 |
| H01L29/152 | 44 |