FinFET having superlattice stressor

Patent metadata

Field	Value
Publication number	US-8994002-B2
Application number	US-201213422531-A
Country	US
Kind code	B2
Filing date	Mar 16, 2012
Priority date	Mar 16, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET) device, comprising:
a superlattice layer disposed over a fin portion of a substrate, the superlattice layer comprising alternating first semiconductor layers and second semiconductor layers, the first semiconductor layers each having a first atomic composition, and the second semiconductor layers each having a second atomic composition different from the first atomic composition, the substrate having a third atomic composition in the fin portion, the first atomic composition and the second atomic composition each being different from the third atomic composition, at least one of the first semiconductor layers or the second semiconductor layers being relaxed; and
a strained layer disposed over the superlattice layer and providing a gate channel, the gate channel stressed by a lattice mismatch with at least one of the first semiconductor layers or the second semiconductor layers of the superlattice layer.

2. The device of claim 1 , wherein the first atomic composition is a first silicon germanium alloy, and the second atomic composition is a second silicon germanium alloy.

3. The device of claim 1 , wherein the first atomic composition is a first III-V semiconductor material, and the second atomic composition is a III-V second semiconductor material.

4. The device of claim 1 , wherein the superlattice layer is disposed in a v-groove of the substrate.

5. The device of claim 1 , wherein the superlattice layer engages the substrate at a ( 111 ) surface of the substrate.

6. The device of claim 1 , wherein the superlattice layer is embedded in a shallow trench isolation (STI) region.

7. The device of claim 1 , wherein the superlattice layer is embedded in a shallow trench isolation (STI) region and the strained layer projects above the STI region.

8. The device of claim 1 , wherein the superlattice layer generates tensile stress in the gate channel.

9. The device of claim 1 , wherein the superlattice layer is configured to reduce emitting stacking faults.

10. The device of claim 1 , wherein the strained layer is configured to enhance mobility of the gate channel.

11. The device of claim 1 further comprising a gate stack over the strained layer.

12. The device of claim 1 , wherein the strained layer is vertically stacked upon the superlattice layer.

13. A field effect transistor (FinFET) device, comprising:
a superlattice layer disposed over a fin portion of a substrate, the superlattice layer comprising alternating first semiconductor layers and second semiconductor layers, a material of the first semiconductor layers being different from a material of the second semiconductor layers, a material of the fin portion of the substrate being different from each of the material of the first semiconductor layers and the material of the second semiconductor layers, at least one of the first semiconductor layers or the second semiconductor layers being relaxed;
a shallow trench isolation (STI) region encapsulating the superlattice layer;
a strained layer disposed over the superlattice layer and providing a gate channel, the gate channel stressed by a lattice mismatch with at least one of the first semiconductor layers or the second semiconductor layers of the superlattice layer; and
a gate stack formed over the strained layer.

14. The device of claim 13 , wherein the material of the first semiconductor layers is a first III-V semiconductor material, and the material of the second semiconductor layers is a second III-V semiconductor material.

15. The device of claim 13 , wherein the material of the first semiconductor layers is a first silicon germanium alloy, and the material of the second semiconductor layers is a second silicon germanium alloy.

16. A method of forming a stressor for a fin field effect transistor (FinFET) device, comprising:
constructing alternating first semiconductor layers and second semiconductor layers of a superlattice layer over a fin portion of a substrate, the first semiconductor layers each having a first atomic composition, and the second semiconductor layers each having a second atomic composition different from the first atomic composition, the fin portion of the substrate having a third atomic composition different from both the first atomic composition and the second atomic composition, at least one of the first semiconductor layers or the second semiconductor layers being relaxed; and
forming a strained layer over the superlattice layer, the strained layer providing a gate channel, the gate channel stressed by a lattice mismatch with at least one of the first semiconductor layers or the second semiconductor layers of the superlattice layer.

17. The method of claim 16 , wherein the first atomic composition is a first III-V semiconductor material, and the second atomic composition is a second III-V semiconductor material.

18. The method of claim 16 , wherein the first atomic composition is a first silicon germanium alloy, and the second atomic composition is a second silicon germanium alloy.

19. The method of claim 16 , further comprising encapsulating the superlattice layer with a shallow trench isolation (STI) region.

20. The method of claim 16 , further comprising forming a gate stack over the strained layer.

Assignees

• Lee Yi-Jing
• Lin You-Ru
• Wan Cheng-Tien
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Taiwan Semiconductor Mfg

Inventors

• Lee Yi-Jing
• Lin You-Ru
• Wan Cheng-Tien
• Wu Cheng-Hsien
• Ko Chih-Hsin

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D62/82

  Heterojunctions · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title