Complementary metal-oxide-semiconductor image sensor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9537040-B2
Application number	US-201313891153-A
Country	US
Kind code	B2
Filing date	May 9, 2013
Priority date	May 9, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.

First claim

What is claimed is:

1. A complementary metal-oxide-semiconductor (CMOS) image sensor comprising:
a substrate having a pixel region and a periphery region defined thereon;
a plurality of photosensitive elements formed in the pixel region;
a first transistor positioned in the pixel region and electrically connected to one of the plurality of photosensitive elements;
a second transistor positioned in the periphery region, and the second transistor comprising a gate electrode and a source/drain;
a first conductive body positioned on the substrate in the pixel region, a top surface of the first conductive body is higher than a surface of the substrate, the first conductive body contacts the one of the plurality of photosensitive elements and protrudes from a surface of the one of the plurality of photosensitive elements;
a first salicide layer formed on the first conductive body, the first salicide layer comprising an inverted-U shape, the first salicide layer being spaced apart from the one of the plurality of photosensitive elements by the first conductive body;
a second salicide layer formed on the source/drain of the second transistor in the periphery region, and the second salicide layer directly contacting the source/drain of the second transistor; and
at least a contact plug formed on and electrically connected to the first salicide, wherein a surface of the contact plug which is in direct contact with a top surface of the first silicide layer has a width less than a width of the first salicide layer, and the first salicide layer and the first conductive body being sandwiched in between the contact plug and the one of the plurality of photosensitive elements in the substrate.

2. The CMOS image sensor according to claim 1 , wherein the first transistor further comprises:
a second conductive body positioned on a gate electrode of the first transistor; and
a third salicide layer formed on the second conductive body, the third salicide layer comprising an inverted-U shape.

3. The CMOS image sensor according to claim 2 , wherein the first conductive body, the second conductive body, and the gate electrode of the first transistor comprise a same material.

4. The CMOS image sensor according to claim 2 , wherein the first conductive body and the second conductive body comprise a material different from the gate electrode of the first transistor.

5. The CMOS image sensor according to claim 2 , further comprising:
a fourth salicide layer formed on the gate electrode of the second transistor.

6. The CMOS image sensor according to claim 5 , wherein the first salicide layer, the second salicide layer, the third salicide layer, and the fourth salicide layer are all non-coplanar.

7. The CMOS image sensor according to claim 6 , wherein a topmost surface of the first salicide layer is higher than a surface of the second salicide layer.

8. The CMOS image sensor according to claim 6 , wherein a topmost surface of the third salicide layer is higher than a surface of the fourth salicide layer.

Assignees

• United Microelectronics Corp

Inventors

• Kao Ching-Hung

Classifications

• H01L27/14643

  Electricity · mapped topic

• H01L27/14609

  Electricity · mapped topic

• H01L31/1804 Primary

  Electricity · mapped topic

• H01L27/14689

  Electricity · mapped topic

• H10F71/121

  The active layers comprising only Group IV materials · CPC title