Three-dimensional memory device containing drain-select-level air gap and methods of making the same

Patent metadata

Field	Value
Publication number	US-10741576-B2
Application number	US-201816136686-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Aug 20, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and word lines located over a substrate;
memory stack structures extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film;
drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction;
a dielectric cap layer located between adjacent drain select gate electrodes, wherein an air gap is located between adjacent drain select gate electrodes in the dielectric cap layer; and
drain-select-level pillar structures located on a respective one of the memory stack structures;
wherein:
each of the drain-select-level pillar structures comprises a drain-select-level channel which contacts an underlying one of the memory stack structures;
the dielectric cap layer comprises a planar portion overlying the drain select gate electrodes and downward-protruding rail portions located between neighboring pairs of the drain select gate electrodes; and
each of the downward-protruding rail portions comprises the air gap which is a cavity that is free of any solid phase material or any liquid phase material.

2. The three-dimensional memory device of claim 1 , wherein each cavity within the downward-protruding rail portions is a laterally undulating cavity that generally extends along the first horizontal direction and has a lateral undulation along the second horizontal direction.

3. The three-dimensional memory device of claim 2 , wherein each cavity within the downward-protruding rail portions includes an upper portion having a variable width that decreases with a vertical distance from the substrate.

4. The three-dimensional memory device of claim 1 , wherein each of the drain-select-level pillar structures comprises:
a cylindrical gate dielectric laterally surrounding the drain-select-level channel; and
a cylindrical gate electrode laterally surrounding the cylindrical gate dielectric.

5. The three-dimensional memory device of claim 4 , wherein each drain select gate electrode comprises a respective cylindrical gate electrode which contacts a respective drain-select-level electrode strip.

6. The three-dimensional memory device of claim 5 , wherein each of the downward-protruding rail portions contacts two rows of dielectric cylindrical segments that are arranged along the first horizontal direction.

7. The three-dimensional memory device of claim 6 , wherein the cylindrical gate electrodes comprise:
first cylindrical gate electrodes that contacts a respective one of the dielectric cylindrical segments on one side and contacting a respective drain-select-level electrode strip; and
second cylindrical gate electrodes that do not contact any of the dielectric cylindrical segments and is laterally surrounded by the drain-select-level electrode strip.

8. The three-dimensional memory device of claim 5 , wherein:
each of the cylindrical gate electrodes comprises a doped semiconductor material; and
each of the drain-select-level electrode strips comprises a metallic material.

9. The three-dimensional memory device of claim 5 , further comprising a dielectric etch stop layer located between the alternating stack and the drain-select-level electrode strips, wherein each drain-select-level channel extends through a respective opening through the dielectric etch stop layer.

10. The three-dimensional memory device of claim 9 , wherein each of the downward-protruding rail portions of the dielectric cap layer includes a pair of sidewalls and a bottom portion that contacts a top surface of the dielectric etch stop layer, wherein a thickness of the bottom portion increases with a lateral distance from a proximal one of the pair of sidewalls.

Assignees

• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Nishida Akio

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title