Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure

Patent metadata

Field	Value
Publication number	US-9646975-B2
Application number	US-201514859525-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Sep 21, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack,

wherein:
each of the electrically conductive layers comprises a cobalt portion having a first side facing the memory stack structures and a cobalt-semiconductor alloy portion in contact with a second side of the cobalt portion;
the cobalt-semiconductor alloy portions have a variable thickness of which a minimum is located between a respective topmost surface thereof and a respective bottommost surface thereof; and
each cobalt portion has a convex sidewall that contacts a concave sidewall of a respective cobalt-semiconductor alloy portion.

2. The three-dimensional memory device of claim 1 , further comprising:
a backside trench that extends through the alternating stack;
an insulating spacer located within the backside trench;
a contact via structure surrounded by the insulating spacer, wherein the cobalt-semiconductor alloy portion is in contact with the insulating spacer.

3. The three-dimensional memory device of claim 2 , wherein:
an interface between the cobalt-semiconductor alloy portion and the insulating spacer is within a vertical plane; and
the interface between the cobalt-semiconductor alloy portion and the insulating spacer is laterally recessed from another vertical plane including sidewalls of the insulating layers.

4. The three-dimensional memory device of claim 1 , wherein each electrically conductive layer further comprises a metallic liner contacting a respective cobalt portion and a respective cobalt-semiconductor alloy portion.

5. The three-dimensional memory device of claim 4 , wherein:
the metallic liner contacts a vertical sidewall surface, a planar top surface, and a planar bottom surface of the respective cobalt portion;
the metallic liner contacts a top surface and a bottom surface of a respective cobalt-semiconductor alloy portion; and
the metallic liner comprises at least one of a conductive metallic nitride and a conductive metallic carbide.

6. The three-dimensional memory device of claim 5 , wherein the metallic liner laterally extends farther outward from the memory stack structures than an outer sidewall of a respective cobalt-semiconductor alloy portion that the metallic liner contacts.

7. The three-dimensional memory device of claim 1 , wherein:
the cobalt portions consist essentially of cobalt; and
the cobalt-semiconductor alloy portions comprise cobalt silicide.

8. The three-dimensional memory device of claim 1 , wherein each of the memory stack structures comprises, from inside to outside:
a semiconductor channel;
a tunneling dielectric layer laterally surrounding the semiconductor channel; and
a vertical stack of charge storage regions laterally surrounding the tunneling dielectric layer.

9. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

10. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack,

wherein:
each of the electrically conductive layers comprises a cobalt portion having a first side facing the memory stack structures and a cobalt-semiconductor alloy portion in contact with a second side of the cobalt portion;
each electrically conductive layer further comprises a metallic liner contacting a respective cobalt portion and a respective cobalt-semiconductor alloy portion;
the metallic liner contacts a vertical sidewall surface, a planar top surface, and a planar bottom surface of the respective cobalt portion;
the metallic liner contacts a top surface and a bottom surface of a respective cobalt-semiconductor alloy portion; and
the metallic liner comprises at least one of a conductive metallic nitride and a conductive metallic carbide.

11. The three-dimensional memory device of claim 10 , further comprising:
a backside trench that extends through the alternating stack;
an insulating spacer located within the backside trench;
a contact via structure surrounded by the insulating spacer, wherein the cobalt-semiconductor alloy portion is in contact with the insulating spacer.

12. The three-dimensional memory device of claim 11 , wherein:
an interface between the cobalt-semiconductor alloy portion and the insulating spacer is within a vertical plane; and
the interface between the cobalt-semiconductor alloy portion and the insulating spacer is laterally recessed from another vertical plane including sidewalls of the insulating layers.

13. The three-dimensional memory device of claim 10 , wherein:
the cobalt-semiconductor alloy portions have a variable thickness of which a minimum is located between a respective topmost surface thereof and a respective bottommost surface thereof; and
each cobalt portion has a convex sidewall that contacts a concave sidewall of a respective cobalt-semiconductor alloy portion.

14. The three-dimensional memory device of claim 10 , wherein the metallic liner laterally extends farther outward from the memory stack structures than an outer sidewall of a respective cobalt-semiconductor alloy portion that the metallic liner contacts.

15. The three-dimensional memory device of claim 10 , wherein:
the cobalt portions consist essentially of cobalt; and
the cobalt-semiconductor alloy portions comprise cobalt silicide.

16. The three-dimensional memory device of claim 10 , wherein each of the memory stack structures comprises, from inside to outside:
a semiconductor channel;
a tunneling dielectric layer laterally surrounding the semiconductor channel; and
a vertical stack of charge storage regions laterally surrounding the tunneling dielectric layer.

17. The three-dimensional memory device of claim 10 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends su

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Peri Somesh
• Koka Sateesh
• Makala Raghuveer S

Classifications

• H01L27/11578

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/115 Primary

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title