Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof

Patent metadata

Field	Value
Publication number	US-9397093-B2
Application number	US-201313762988-A
Country	US
Kind code	B2
Filing date	Feb 8, 2013
Priority date	Feb 8, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material, etching the stack to form a front side opening in the stack, selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions on portions of the second material layers exposed in the front side opening, forming a tunnel dielectric layer and semiconductor channel layer in the front side opening, etching the stack to form a back side opening in the stack, removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers, forming a blocking dielectric in the back side recesses through the back side opening, and forming control gates over the blocking dielectric in the back side recesses through the back side opening.

First claim

What is claimed is:

1. A method of making a monolithic three dimensional NAND string, comprising:
forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises an electrically insulating material and wherein the second material comprises a sacrificial material;
etching the stack to form a front side opening in the stack;
selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions on portions of the second material layers exposed in the front side opening;
forming a tunnel dielectric layer over the charge storage regions in the front side opening;
forming a semiconductor channel layer over the tunnel dielectric layer in the front side opening;
etching the stack to form a back side opening in the stack;
removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers;
forming a blocking dielectric in the back side recesses through the back side opening; and
forming control gates over the blocking dielectric in the back side recesses through the back side opening,
wherein the step of selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions comprises selectively growing metal or silicide charge storage regions on the portions of the second material layers exposed in the front side opening.

2. The method of claim 1 , wherein the second material comprises polysilicon or amorphous silicon.

3. The method of claim 2 , wherein the second material comprises intrinsic or undoped polyliscon and the charge storage regions comprise polysilicon regions.

4. The method of claim 3 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions comprises selectively growing doped polysilicon regions on the portions of the second material layer exposed in the front side opening.

5. The method of claim 4 , wherein the doped polysilicon regions comprise boron doped, p-type polysilicon regions and wherein the doped polysilicon regions are not grown on portions of the first material layers exposed in the front side opening.

6. The method of claim 3 , wherein the step of selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions comprises doping the portions of the second material layer exposed in the front side opening.

7. The method of claim 3 , further comprising:
forming a metal layer through the back side opening in the back side recesses in contact with the polysilicon charge storage regions after the step of removing at least a portion of the second material layers removes all second material layers to expose the polysilicon charge storage regions in the back side recesses;
reacting the metal layer with the polysilicon charge storage regions to convert the polysilicon charge storage regions to silicide charge storage regions; and
selectively removing unreacted portions of the metal layer without removing the silicide charge storage regions.

8. The method of claim 3 , further comprising:
forming a metal layer through the back side opening in the back side recesses in contact with remaining portions of the second material layers remaining after the step of removing at least a portion of the second material layers;
reacting the metal layer with the remaining portions to form discrete silicide regions in the back side recesses in contact with the charge storage regions; and
selectively removing unreacted portions of the metal layer without removing the silicide regions.

9. The method of claim 2 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions comprises:
forming a metal layer in the front side opening;
reacting the metal layer with the portions of the second material layer exposed in the front side opening to form discrete silicide charge storage regions; and
selectively removing unreacted portions of the metal layer without removing the discrete silicide charge storage regions.

10. The method of claim 1 , further comprising nitriding the plurality of discrete semiconductor, metal or silicide charge storage regions to form nitrided charge storage regions.

11. The method of claim 1 , further comprising forming a silicon nitride charge storage layer in the front side opening in contact with the plurality of discrete semiconductor, metal or silicide charge storage regions to form a hybrid charge storage structure.

12. The method of claim 1 , further comprising recessing the second material layers in the front side opening to form front side recesses, such that the step of selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions selectively forms the plurality of discrete semiconductor, metal or silicide charge storage regions in the front side recesses.

13. The method of claim 1 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions selectively forms the plurality of discrete semiconductor, metal or silicide charge storage regions which protrude into the front side opening.

14. The method of claim 1 , wherein:
at least one end portion of the semiconductor channel extends vertically in a substantially perpendicular direction to a major surface of the substrate; and
the plurality of discrete semiconductor, metal or silicide charge storage regions comprise a plurality of vertically spaced apart floating gates.

15. The method of claim 12 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions selectively forms the plurality of discrete semiconductor, metal or silicide charge storage regions in the front recesses such that a plurality of discrete semiconductor, metal or silicide charge storage regions protrude into the front side opening.

16. The method of claim 12 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions selectively forms the plurality of discrete semiconductor, metal or silicide charge storage regions in the front recesses such that edges of the plurality of discrete semiconductor, metal or silicide charge storage regions are substantially even with edges of the first material in the front side opening.

17. The method of claim 12 , wherein the step of selectively forming the plurality of discrete semiconductor, metal or silicide charge storage regions selectively grows the plurality of discrete semiconductor, metal or silicide charge storage regions on the portions of the second material layers exposed in the front recesses in the front side opening but not on portions of the first material layers exposed in the front side opening.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Makala Raghuveer S
• Alsmeier Johann

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title