Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks

Patent metadata

Field	Value
Publication number	US-9449982-B2
Application number	US-201514748808-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Mar 12, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

First claim

What is claimed is:

1. A method of making a vertical NAND device, comprising:
forming a lower portion of a memory stack over a substrate;
forming a lower portion of memory openings in the lower portion of the memory stack;
partially filling each lower portion of the memory openings with a sacrificial material to leave an air gap in each lower portion of the memory openings below the sacrificial material;
forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material;
forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings;
removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings extending through the upper and the lower portions of the memory stack; and
forming a semiconductor channel in each continuous memory opening.

2. The method of claim 1 , wherein partially filling each lower portion of the memory openings with a sacrificial material to leave an air gap in each lower portion of the memory openings below the sacrificial material comprises forming a sacrificial material portion having the air gap comprising an encapsulated cavity therein within each lower portion of the memory openings.

3. The method of claim 2 , wherein the sacrificial material portions comprise a semiconductor material.

4. The method of claim 3 , wherein the semiconductor material comprises amorphous silicon deposited by plasma enhanced chemical vapor deposition.

5. The method of claim 3 , wherein the semiconductor material of the sacrificial material portion is located over bottom and side surfaces of each lower portion of the memory openings.

6. The method of claim 5 , wherein:
each encapsulated cavity consists of a volume defined by the inner surfaces of a respective sacrificial material portion that are spaced from outer surfaces of the respective sacrificial material portion; and
the inner surfaces of the respective sacrificial material portion form top, bottom and side surfaces of the encapsulated cavity.

7. The method of claim 2 , further comprising forming an epitaxial pedestal comprising a single crystalline material on a physically exposed semiconductor surface of the substrate at a bottom of each lower portion of memory openings.

8. The method of claim 7 , further comprising converting an upper portion of each epitaxial pedestal into a semiconductor oxide portion, wherein each sacrificial material portion is formed directly on an underlying semiconductor oxide portion.

9. The method of claim 8 , wherein each semiconductor oxide portion is a silicon oxide portion.

10. The method of claim 7 , further comprising forming a stack of material layers in each memory opening, wherein the stack of material layers comprises:
a blocking dielectric layer deposited on sidewalls of the memory openings;
a charge storage layer deposited on the blocking dielectric layer; and
a tunneling dielectric layer deposited on the charge storage layer.

11. The method of claim 10 , wherein:
the stack of material layers further comprises a first semiconductor channel layer comprising a semiconductor material and deposited on the tunneling dielectric layer; and
the method further comprises forming an opening through the stack of material layers underneath each contiguous memory opening by removing horizontal portions of the stack of material layers underneath each contiguous memory opening by an anisotropic etch.

12. The method of claim 11 , further comprising removing a center portion of each semiconductor oxide portion after forming the openings through the stack of material layers.

13. The method of claim 12 , wherein a remaining portion of each semiconductor oxide portion has an annular shape.

14. The method of claim 12 , further comprising:
filling each contiguous memory opening with an additional semiconductor material after removing center portions of the semiconductor oxide portions; and
removing portions of the additional semiconductor material from above a horizontal plane including a top surface of the upper portion of the memory stack,
wherein each remaining portion of the first semiconductor channel layer and the additional semiconductor material constitutes the semiconductor channel.

15. The method of claim 1 , wherein:
the lower and the upper portions of the memory stack comprise alternating insulating and sacrificial layers;
the sacrificial material layers are removed and replaced with control gate electrodes; and
the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.

16. The method of claim 15 , further comprising forming a memory film which comprises at least one charge storage region located between blocking and tunneling dielectric layers in each continuous memory opening prior to the step of forming the semiconductor channel.

17. The method of claim 16 , wherein:
the tunnel dielectric layer is located adjacent to the semiconductor channel;
the charge storage region is located adjacent to the tunnel dielectric layer; and
the blocking dielectric layer is located adjacent to the charge storage region.

18. The method of claim 17 , wherein:
the control gate electrodes comprise, or are, electrically connected to a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

19. The method of claim 1 , wherein the lower and the upper portions of the memory stack comprise alternating insulating and control gate material layers.

20. The method of claim 1 , wherein the lower portion of the memory openings is formed by etching the lower portion of the memory stack using a first hard mask, and the upper portion of the memory openings is formed by etching the upper portion of the memory stack using at least one second hard mask.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lu Zhenyu
• Koka Sateesh
• Kai James
• Makala Raghuveer S
• Lee Yao-Sheng
• Pachamuthu Jayavel
• Alsmeier Johann
• Chien Henry

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title