Semiconductor device with air-spacer

Patent metadata

Field	Value
Publication number	US-10522642-B2
Application number	US-201715623539-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Dec 14, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

First claim

What is claimed is:

1. A method, comprising:
forming a gate structure on a substrate;
forming a seal spacer covering a sidewall of the gate structure;
forming a sacrificial spacer covering a sidewall of the seal spacer;
forming source/drain (S/D) regions sandwiching a channel region that is under the gate structure;
depositing a contact etch stop (CES) layer covering a sidewall of the sacrificial spacer;
forming a dielectric layer on the gate structure, the sacrificial spacer and the CES layer;
with the dielectric layer on the gate structure, the sacrificial spacer and the CES layer, forming a contact extending through the dielectric layer to a first S/D region of the S/D regions, wherein a top surface of the contact is above a top surface of the gate structure;
removing the dielectric layer to expose the sacrificial spacer;
removing the sacrificial spacer to form a trench, wherein the trench spans from a sidewall of the CES layer to the sidewall of the seal spacer; and
depositing an inter-layer dielectric (ILD) layer, wherein the ILD layer caps the trench, thereby defining an air gap inside the trench, wherein the air gap spans from the sidewall of the CES layer to the sidewall of the seal spacer, and wherein the seal spacer is in physical contact with the ILD layer and entirely spaced away from the CES layer.

2. The method of claim 1 , wherein the removing of the sacrificial spacer includes an etching process that exposes a top surface of the channel region, wherein the air gap spans vertically from the top surface of the channel region to a bottom surface of the ILD layer.

3. The method of claim 1 , wherein the removing of the sacrificial spacer includes an etching process that keeps a portion of the sacrificial spacer covering a bottom surface of the trench, wherein the air gap spans vertically from a top surface of the portion of the sacrificial spacer to a bottom surface of the ILD layer.

4. The method of claim 1 , wherein:
each of the seal spacer and the CES layer includes nitride; and
the seal spacer and the CES layer include different material compositions.

5. The method of claim 4 , wherein each of the seal spacer and the CES layer includes a composition selected from a group of silicon nitride, silicon carbonitride, silicon carbon oxynitride, and a combination thereof.

6. The method of claim 4 , wherein the sacrificial spacer includes aluminum oxide.

7. The method of claim 4 , wherein the ILD layer includes oxide.

8. The method of claim 1 , wherein the ILD layer extends laterally from the air gap to a top surface of the seal spacer and directly contacts the top surface of the seal spacer.

9. The method of claim 1 , wherein the forming of the contact extending through the dielectric layer includes:
patterning the dielectric layer to form a via hole exposing the first S/D region; and
forming the contact in the via hole.

10. The method of claim 9 , further comprising:
prior to the forming of the dielectric layer, performing a first chemical mechanical planarization (CMP) process to expose the gate structure; and
after the depositing of the ILD layer, performing a second CMP process to the ILD layer to expose the contact.

11. A method of forming a semiconductor device, the method comprising:
forming a gate stack on a semiconductor substrate;
forming a seal spacer covering a sidewall of the gate stack;
forming a sacrificial spacer covering a sidewall of the seal spacer;
forming source/drain (S/D) regions interposed by a channel region that is under the gate stack;
forming a contact etch stop (CES) layer over the sacrificial spacer and covering a sidewall of the sacrificial spacer;
depositing a first inter-layer dielectric (ILD) layer over the gate stack, the sacrificial spacer and CES layer;
patterning the first ILD layer, thereby forming an opening exposing one of the S/D regions;
with the first ILD layer over the gate stack, the sacrificial spacer and the CES layer, forming an S/D contact in the opening;
thereafter removing the first ILD layer to expose the sacrificial spacer;
removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the CES layer and the sidewall of the seal spacer; and
depositing a second ILD layer over the S/D contact, the seal spacer, and the gate stack, wherein the second ILD layer seals the trench and is in physical contact with the seal spacer, thereby defining a void inside the trench.

12. The method of forming the semiconductor device of claim 11 , wherein the void exposes a top surface of the semiconductor substrate.

13. The method of forming the semiconductor device of claim 11 , wherein:
each of the seal spacer and the CES layer includes nitride; and
each of the sacrificial spacer and the second ILD layer includes oxide.

14. The method of forming the semiconductor device of claim 13 , wherein:
the seal spacer contains silicon carbonitride;
the CES layer contains silicon carbon oxynitride;
the sacrificial spacer contains aluminum oxide; and
the second ILD layer contains silicon oxide.

15. The method of forming the semiconductor device of claim 11 , wherein a top surface of the S/D contact is above a top surface of the gate stack.

16. A semiconductor device, comprising:
a substrate having source/drain (S/D) regions with a channel region interposed therebetween;
a gate stack over the channel region, the gate stack including a gate dielectric layer and a gate electrode layer;
a spacer layer covering sidewalls of the gate stack;
an S/D contact metal over one of the S/D regions, wherein the S/D contact metal extends above a top surface of the gate electrode layer and below a bottom surface of the gate dielectric layer;
a contact etch stop (CES) layer covering sidewalls of the S/D contact metal, wherein the CES layer has a first portion and a second portion containing same material, the first portion and the second portion of the CES layer are in direct contact with the sidewalls of the S/D contact metal and the S/D contact metal is disposed between the first portion and the second portion of the CES layer, wherein top surfaces of the first portion and the second portion of the CES layer and the top surface of the gate electrode layer are planarized; and
an inter-layer dielectric (ILD) layer covering the first portion and the second portion of the CES layer, the spacer layer, and the gate stack, wherein the first portion and the second portion of the CES layer and the spacer layer are spaced from each other and free of physical contact, defining a gap spanning from a sidewall of the first portion or the second portion of the CES layer to a sidewall of the spacer layer, the gap being capped by the ILD layer, the ILD layer being in physical contact with the spacer layer, and the top surface of the gate electrode layer.

17. The semiconductor device of claim 16 , wherein the gap spans vertically from a top surface of the channel region to a bottom surface of the ILD layer.

18. The semiconductor device of claim 16 , further comprising:
a dielectric layer above the substrate and interposed between the spacer layer and the CES layer, wherein the gap spans vertically from a top surface of the dielectric layer to a bottom surface of the ILD layer.

19. The semiconductor device of claim 18 , wherein the dielectric layer is aluminum oxide.

20. The semiconductor device of claim 16 , wherein:
the ILD layer contains silicon oxide;
each of the spacer layer and the first portion and the second portion of the C

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Wei-Yang
• Yang Feng-Cheng
• Lin Chung-Te
• Chen Yen-Ming

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title