Heterogeneous source drain region and extension region

Patent metadata

Field	Value
Publication number	US-2016013313-A1
Application number	US-201414330158-A
Country	US
Kind code	A1
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A semiconductor structure includes a source drain region of a first material that may fulfill contact resistance and doping requirements and an extension region of a second material with increased mobility and dopant concentration. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by vertically removing the sacrificial dielectric portion accessible via the replacement gate trench and horizontally removing the sacrificial dielectric portion beneath the spacer, and forming an extension region of a second doped material within the extension trench.

First claim

The invention claimed is:

1 . A semiconductor device fabrication process comprising:
forming a sacrificial dielectric portion upon a semiconductor substrate; forming a sacrificial gate stack upon the sacrificial dielectric portion; forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate; forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer; forming a replacement gate trench by removing the sacrificial gate stack; forming an extension trench by vertically removing the sacrificial dielectric portion accessible via the replacement gate trench and horizontally removing the sacrificial dielectric portion beneath the spacer, and; forming an extension region of a second doped material within the extension trench.

2 . The semiconductor fabrication process of claim 1 , further comprising:
forming an interlayer dielectric portion upon the source drain region against the gate spacer.

3 . The semiconductor fabrication process of claim 1 , further comprising:
forming a high-k dielectric liner within the replacement gate trench.

4 . The semiconductor fabrication process of claim 3 , further comprising:
forming a replacement gate within the replacement gate trench.

5 . The semiconductor fabrication process of claim 4 , further comprising:
forming a planarization dielectric layer upon the interlayer dielectric portion, upon an upper surface of the gate spacer, upon an upper surface of the high-k dielectric liner, and upon the replacement gate.

6 . The semiconductor fabrication process of claim 5 , further comprising:
forming a source drain contact trench within the planarization dielectric layer and within the interlayer dielectric portion to expose the source drain region, and; forming a source drain contact by filling the source drain contact trench with electrically conductive material.

7 . The semiconductor fabrication process of claim 6 , further comprising:
forming a channel contact trench within the planarization dielectric layer to expose the source drain region, and; forming a channel contact by filling the channel contact trench with electrically conductive material.

8 . The semiconductor fabrication process of claim 1 , wherein the sacrificial gate stack comprises a sacrificial gate formed upon the sacrificial dielectric portion and a sacrificial gate cap formed upon the sacrificial gate.

9 . The semiconductor fabrication process of claim 1 , wherein the gate spacer is a sacrificial gate spacer.

10 . The semiconductor fabrication process of claim 9 , further comprising:
removing the sacrificial gate spacer, and; forming a replacement gate spacer prior to forming the replacement gate trench.

11 . The semiconductor fabrication process of claim 10 , wherein the replacement gate spacer is a low-k dielectric.

12 . The semiconductor fabrication process of claim 1 , wherein the semiconductor substrate is a multilayered semiconductor substrate.

13 . The semiconductor fabrication process of claim 1 , wherein the semiconductor substrate is a bulk semiconductor substrate.

14 . The semiconductor fabrication process of claim 1 , wherein the second doped material comprises a higher dopant concentration relative to the first doped material.

15 . The semiconductor fabrication process of claim 1 , wherein the extension region is electrically contacting the source drain region.

16 . A semiconductor device comprising:
a source drain region of a first doped material upon a semiconductor; an extension region of a second doped material upon the semiconductor against the source drain region, and; a replacement gate adjacent to the extension region.

17 . The semiconductor device of claim 16 , wherein the second doped material comprises a higher dopant concentration relative to the first doped material.

18 . The semiconductor device of claim 16 , further comprising:
a gate spacer upon the extension region against source drain region and against the replacement gate.

19 . A design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a source drain region of a first doped material upon a semiconductor; an extension region of a second doped material upon the semiconductor against the source drain region, and; a replacement gate adjacent to the extension region.

20 . The design structure of claim 19 , wherein the second doped material comprises a higher dopant concentration relative to the first doped material.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title