Transistor with SiCN/SiOCN mulitlayer spacer

Patent metadata

Field	Value
Publication number	US-9685533-B1
Application number	US-201615049133-A
Country	US
Kind code	B1
Filing date	Feb 21, 2016
Priority date	Feb 21, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a gate structure on said substrate;
two spacers on both sidewalls of said gate structure, wherein each said spacer comprises an inner first spacer portion primarily made of SiCN directly contacting said gate structure and an outer second spacer portion primarily made of SiOCN, wherein the oxygen concentration of each said outer second spacer is gradually increased from the boundary between said first spacer portion and said second portion to the outer surface of said second spacer portion; and
two epitaxial structures as source/drain at both sides of said two spacers.

2. The semiconductor device of claim 1 , wherein said first spacer portion is L-shaped with a vertical section between said second spacer portion and said gate structure and a horizontal section between said second spacer portion and said substrate.

3. The semiconductor device of claim 1 , wherein said first spacer portion and said second spacer portion are made of multilayer films with gradient concentrations of oxygen increasing from the boundary between said first spacer portion and said gate structure to the outer surface of said second spacer portion.

4. The semiconductor device of in claim 1 , further comprising a fin type active pattern protruding from said substrate, and said gate structure, said two spacers and said two epitaxial structures are formed on said fin type active pattern.

5. The semiconductor device of claim 1 , wherein said gate structure comprises a gate insulating layer, a work function layer and a metal layer.

6. The semiconductor device of claim 1 , further comprising a blocking film formed on said gate structure, said two spacers and said two epitaxial structures.

Assignees

• United Microelectronics Corp

Inventors

• Kuo Chia-Ming
• Chuang Po-Jen
• Chuang Fu-Jung
• Wen Tsai-Yu
• Lu Tsuo-Wen
• Wang Yu-Ren
• Tsai Fu-Yu

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title