Air gap spacer between contact and gate region

Patent metadata

Field	Value
Publication number	US-9716158-B1
Application number	US-201615076362-A
Country	US
Kind code	B1
Filing date	Mar 21, 2016
Priority date	Mar 21, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Unfilled gaps are provided as spacers between gate stacks and electrically conductive source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers are removed partially or entirely from portions of the gate stacks and replaced by materials such as amorphous semiconductor materials. Source/drain contacts subsequently formed on source/drain regions adjoin the spacer replacement material. Selective removal of the spacer replacement material leaves unfilled gaps between the source/drain contacts and the gate stacks. The unfilled gaps are then sealed by a dielectric layer that leaves the gaps substantially unfilled.

First claim

What is claimed is:

1. A method comprising:
obtaining a structure including:
a plurality of field-effect transistors, each field-effect transistor including a channel region, a gate stack adjoining the channel region, source/drain regions adjoining the channel region, and sidewall spacers lining first and second sidewalls of the gate stack,
a dielectric layer overlying the gate stacks, and
trenches within the dielectric layer, the trenches exposing a plurality of the sidewall spacers and a plurality of the source/drain regions;

removing the sidewall spacers at least in part from at least one of the first and second sidewalls of a plurality of the gate stacks;
replacing the removed sidewall spacers with dummy spacers;
forming electrically conductive source/drain contacts on a plurality of the source/drain regions and between pairs of the dummy spacers; and
removing the dummy spacers, thereby forming unfilled gaps between the source/drain contacts and the gate stacks.

2. The method of claim 1 , wherein replacing the sidewall spacers with dummy spacers further includes depositing a strippable layer within the trenches and forming the dummy spacers from the strippable layer, and forming the electrically conductive source/drain contacts further includes depositing contact metal within the trenches after the dummy spacers are formed.

3. The method of claim 2 , further including depositing a sealing layer over the unfilled gaps, thereby sealing the unfilled gaps between the source/drain contacts and the gate stacks.

4. The method of claim 3 , wherein the plurality of field-effect transistors include FinFETs and the source/drain regions include doped epitaxial regions.

5. The method of claim 4 , wherein each trench exposes one of the sidewall spacers of two adjoining gate stacks, the dielectric layer covering another of the sidewall spacers of each two adjoining gate stacks, and further wherein removing the sidewall spacers further includes removing one of the sidewall spacers from the gate stack of each two adjoining gate stacks.

6. The method of claim 5 , wherein the dummy spacers comprise amorphous semiconductor material.

7. The method of claim 1 , wherein removing the sidewall spacers further includes removing the entireties of the sidewall spacers from at least one of the first and second sidewalls of a plurality of the gate stacks.

8. The method of claim 7 , further including forming a second dielectric layer on the at least one of the first and second sidewalls of a plurality of the gate stacks following removing the sidewall spacers and forming the dummy spacers on the second dielectric layers.

9. The method of claim 8 , wherein forming the dummy spacers includes depositing an amorphous semiconductor layer on the structure and subjecting the amorphous semiconductor layer to a directional etch.

10. The method of claim 8 , further including depositing a sealing layer over the unfilled gaps, thereby sealing the unfilled gaps between the source/drain contacts and the gate stacks.

11. The method of claim 10 , wherein forming the electrically conductive source/drain contacts further includes depositing contact metal within the trenches.

12. The method of claim 11 , wherein the plurality of field-effect transistors include FinFETs and the source/drain regions include doped epitaxial regions.

13. A semiconductor structure comprising:
a plurality of field-effect transistors, each field-effect transistor including a channel region, a gate stack adjoining the channel region, and source/drain regions adjoining the channel region;
a dielectric layer overlying the gate stacks;
a plurality of trenches within the dielectric layer;
electrically conductive source/drain contacts within the trenches and on a plurality of the source/drain regions;
the source/drain contacts and the gate stacks being separated by unfilled gaps, the unfilled gaps including sealed upper end portions;
wherein each of the gate stacks includes a first sidewall, a sidewall spacer on the first sidewall, a second sidewall, a sidewall dielectric layer on the second sidewall, the sidewall spacer having a greater thickness than the sidewall dielectric layer, the unfilled gap adjoining the sidewall dielectric layer.

14. The semiconductor structure of claim 13 , wherein the plurality of field-effect transistors include a plurality of FinFETs, the source/drain regions of the FinFETs including doped epitaxial regions.

15. The semiconductor structure of claim 14 , wherein each of the source/drain contacts is positioned between a pair of the gate stacks and adjoins a pair of the unfilled gaps.

16. The semiconductor structure of claim 15 , wherein each of the source/drain contacts includes a contact metal comprising tungsten.

17. The semiconductor structure of claim 15 , wherein each of the unfilled gaps has a width between five and fifteen nanometers.

18. The semiconductor structure of claim 13 , wherein each of the source/drain contacts is positioned between a pair of the gate stacks and adjoins a pair of the unfilled gaps.

19. The semiconductor structure of claim 18 , wherein the sidewall dielectric layer included in each of the gate stacks has a thickness of about two nanometers.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Loubet Nicolas Jean
• Miao Xin
• Reznicek Alexander

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title