Air gap spacer for metal gates

Patent metadata

Field	Value
Publication number	US-9608065-B1
Application number	US-201615173132-A
Country	US
Kind code	B1
Filing date	Jun 3, 2016
Priority date	Jun 3, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

First claim

What is claimed is:

1. A transistor device comprising:
gate structures located between the source and drain regions;
metal contacts formed on the source and drain regions and spaced from the gate structures, wherein the metal contacts have a first width proximate to the source and drain regions that tapers to a larger second width in a direction away from the source and drain regions; and
a substantially conformal dielectric layer present on at least sidewalls of the metal contacts and sidewall of the gate structures, the substantially conformal dielectric layer having a pinched off region that seals air gaps between the metal contacts and the gate structures, the pinched off region being proximate to the second width of the metal contact.

2. The device of claim 1 further comprising an interlayer dielectric material positioned around at least a portion of the gate structures.

3. The device of claim 1 , wherein the device is fin-type field effect transistor (FinFET) further comprising fin structures having a channel region that the gate structures are present on, wherein the source region is present on a source region portion of the fin structure and the drain region is present on a drain region portion of the fin structure.

4. The device of claim 1 , further comprising spacer remnants located adjacent to at least one of the source region and the drain region.

5. The device of claim 1 , further comprising a dielectric cap positioned over the gate structures.

6. The device of claim 1 , wherein the substantially conformal dielectric material is in contact with at least a portion of a gate dielectric for the gate structures.

7. The device of claim 6 , wherein the gate dielectric is a high-k dielectric material.

8. The device of claim 6 , wherein the substantially conformal dielectric material fills recesses present in the gate dielectric adjacent to remnant spacer portions.

9. The device of claim 1 , wherein the gate structure is comprised of a work function metal nitride selected from the group consisting of titanium nitride, ruthenium, titanium aluminum, aluminum nitride, tantalum carbide and combinations thereof.

10. The device of claim 1 , wherein the metal contacts are comprised of a material selected from the group consisting of titanium, aluminum, copper, tungsten, platinum, gold, doped polysilicon and combinations thereof.

11. The device of claim 1 , wherein the substantially conformal dielectric material is a low-k dielectric material selected from the group consisting of: organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics (e.g., SILK™), spin-on silicone based polymeric dielectric, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and combinations thereof.

12. The method of claim 11 , wherein the second spacer material is deposited by chemical vapor deposition.

13. The method of claim 12 , wherein the forming of the sacrificial spacer on the sidewalls of the trench and on the sidewall of the at least one gate structure comprises:
depositing a continuous dielectric material layer on vertical surfaces of the trench sidewall and horizontal surfaces at a base of the trench; and
anisotropically etching the continuous dielectric material to remove the continuous dielectric material from the horizontal surfaces of the trench and to reduce a width of the continuous dielectric material at an upper surface of the vertical surfaces of the trench to provide said sacrificial spacer having an upper surface with a width less than a base surface of the sacrificial spacer.

14. The method of claim 11 , wherein said removing the sacrificial spacer comprises annealing.

15. A method for forming a transistor device comprising:
forming a trench in an interlayer dielectric layer, wherein the trench is adjacent to at least one gate structure to expose an electrical contact surface of one of a source region and a drain region;
forming a sacrificial spacer on sidewalls of the trench, wherein the sacrificial spacer has a base width greater than an upper surface width;
forming a metal contact in the trench on at least one of the source region and the drain region, wherein the metal contact has a base width that is less than an upper surface width of the contact;
removing the sacrificial spacer; and
forming a substantially conformal dielectric material layer on sidewalls of the metal contact and the gate structure exposed by removing the sacrificial spacer, wherein portions of the conformally dielectric material layer contact one another at a pinch off region that is proximate to the upper surface width of the metal contact to form an air gap between the metal contact and the gate structures.

16. The method of claim 15 , wherein said forming the trench in the interlayer dielectric layer comprises:
forming said trench exposing sidewall spacers on adjacent gate structures of said at least one gate structure;
recessing said sidewall spacers to provide remnant spacer portions; and
recessing a vertical portion of a gate dielectric of said adjacent gate structures.

17. The method of claim 16 , wherein recessing said vertical portion of said gate dielectric of said adjacent gate structures recesses are formed between a remaining portion of the gate structure and at least one of the source region and the drain region.

18. The method of claim 16 , wherein the gate structure is present on a channel region portion of a fin structure.

19. The method of claim 16 , wherein the vertical portion of the gate dielectric is removed using isotropic etching.

20. A method for forming a fin field effect transistor (FinFET) device comprising:
forming trenches in an interlayer dielectric layer between metal gate structures, wherein the trenches are over source and drain region portions of a fin structure;
forming a sacrificial spacer on sidewalls of the trench, wherein the sacrificial spacer has a base width greater than an upper surface;
forming a metal contact in the trench in electrical communication with at least one of said source region portion and said drain region portion of the fin structure, wherein the metal contact has a base width that is less than an upper surface width of the contact;
removing the sacrificial spacer; and
forming a substantially conformal dielectric material layer on sidewalls of the metal contact and the gate structure exposed by removing the sacrificial spacer, wherein portions of the conformally dielectric material layer contact one another at a pinch off region that is proximate to the upper surface width of the metal contact to form an air gap entirely filling a space between the metal contact and the gate structures.

Assignees

• IBM

Inventors

• Bergendahl Marc A
• Cheng Kangguo
• Lie Fee Li
• Miller Eric R
• Sporre John R
• Teehan Sean

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/076

  in via holes or trenches · CPC title