Stitching to enable dense interconnect arrangements
US-2026082899-A1 · Mar 19, 2026 · US
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Wei Andy Chih-Hung patents
Wei Andy Chih-Hung is listed as an inventor on 126 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wei Andy Chih-Hung |
| Total patents | 126 |
| First publication | Jul 30, 2015 |
| Latest publication | Mar 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Integrated circuit structures having maximized channel sizing
US-2026026057-A1 · Jan 22, 2026 · US
Stitching to enable dense interconnect arrangements
US-12512407-B2 · Dec 30, 2025 · US
Power rail between fins of a transistor structure
US-12506076-B2 · Dec 23, 2025 · US
Gate tie structures to buried or backside power rails
US-12489057-B2 · Dec 2, 2025 · US
Integrated circuit structures having maximized channel sizing
US-12471330-B2 · Nov 11, 2025 · US
Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures
US-12439659-B2 · Oct 7, 2025 · US
Dual metal gate structures on nanoribbon semiconductor devices
US-12426307-B2 · Sep 23, 2025 · US
Source/drain regions in integrated circuit structures
US-12376353-B2 · Jul 29, 2025 · US
Integrated circuit structures having multi-height cells
US-2025212525-A1 · Jun 26, 2025 · US
Recent patents
Latest publications not already listed above.
Gate spacing in integrated circuit structures
US-12328936-B2 · Jun 10, 2025 · US
Integrated circuit structures with gate cuts above buried power rails
US-12327791-B2 · Jun 10, 2025 · US
Self-aligned lateral contacts
US-12315805-B2 · May 27, 2025 · US
Stacked vias with bottom portions formed using selective growth
US-2025125255-A1 · Apr 17, 2025 · US
Transistor arrangements with stacked trench contacts and gate straps
US-12237388-B2 · Feb 25, 2025 · US
Stacked vias with bottom portions formed using selective growth
US-12211786-B2 · Jan 28, 2025 · US
Device contact sizing in integrated circuit structures
US-12211898-B2 · Jan 28, 2025 · US
Use of a placeholder for backside contact formation for transistor arrangements
US-2025022878-A1 · Jan 16, 2025 · US
Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication
US-12199161-B2 · Jan 14, 2025 · US
Use of a placeholder for backside contact formation for transistor arrangements
US-12148751-B2 · Nov 19, 2024 · US
Buried power rails with self-aligned vias to trench contacts
US-12094822-B2 · Sep 17, 2024 · US
Integrated circuit structures having stacked electrostatic discharge (esd) for backside power delivery
US-2024222360-A1 · Jul 4, 2024 · US
Source/drain regions in integrated circuit structures
US-2024162289-A1 · May 16, 2024 · US
Device contacts in integrated circuit structures
US-11973121-B2 · Apr 30, 2024 · US
Stacked source or drain contact flyover
US-2024113177-A1 · Apr 4, 2024 · US
Source/drain regions in integrated circuit structures
US-11916106-B2 · Feb 27, 2024 · US
Back end of line integration for self-aligned vias
US-11916010-B2 · Feb 27, 2024 · US
Isolation regions in integrated circuit structures
US-11749715-B2 · Sep 5, 2023 · US
Integrated circuit structure with buried power rail
US-2023207465-A1 · Jun 29, 2023 · US
Integrated circuits with self-aligned tub architecture
US-2023207704-A1 · Jun 29, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 70 |
| Globalfoundries Inc | 53 |
| Global Foundries Inc | 3 |
| Intel NDTM US LLC | 2 |
| Lavric Dan S | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 65 |
| H10D30/62 | 64 |
| H10W20/069 | 59 |
| H10D84/834 | 56 |
| H10D30/024 | 48 |