Device contact sizing in integrated circuit structures

Patent metadata

Field	Value
Publication number	US-12211898-B2
Application number	US-202217814364-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Mar 26, 2020
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

First claim

The invention claimed is:

1. An integrated circuit (IC) structure, comprising:
a first gate contact;
a second gate contact adjacent to the first gate contact;
a region between the first gate contact and the second gate contact, wherein the region includes:
a first spacer on the first gate contact, a second spacer on the second gate contact, a third spacer on the first spacer, and a fourth spacer on the second spacer; and
a source/drain (S/D) contact between the third spacer and the fourth spacer; and

a S/D region under the S/D contact, wherein at least a portion of the first spacer and at least a portion of the second spacer are directly over the S/D region.

2. The IC structure of claim 1 , wherein the third spacer and the fourth spacer are portions of a continuous portion of dielectric material.

3. The IC structure of claim 2 , wherein the continuous portion of dielectric material has a U-shaped cross-section.

4. The IC structure of claim 1 , wherein at least one of the spacers has a thickness between 2 nanometers and 10 nanometers.

5. The IC structure of claim 1 , further comprising:
a channel region associated with the first gate contact.

6. The IC structure of claim 5 , wherein the channel region comprises a semiconductor fin.

7. The IC structure of claim 5 , wherein the channel region comprises a semiconductor wire.

8. The IC structure of claim 1 , further comprising a third gate contact adjacent to the second gate contact, and a region between the second gate contact and the third gate contact, the region comprising a fifth spacer on the second gate contact, and a sixth spacer on the third gate contact.

9. The IC structure of claim 8 , further comprising:
a first source/drain (S/D) contact between the third spacer and the fourth spacer; and
a second S/D contact between the fifth spacer and the sixth spacer, the first S/D contact having a smaller length than the second S/D contact.

10. The IC structure of claim 1 , wherein at least a portion of the third spacer and at least a portion of the fourth spacer are over the S/D region.

11. An integrated circuit (IC) structure, comprising:
a first gate contact;
a second gate contact adjacent to the first gate contact;
a third gate contact adjacent to the second gate contact;
a first region extending from the first gate contact to the second gate contact, the first region comprising two spacers on the second gate contact; and
a second region extending from the second gate contact to the third gate contact, the second region comprising a smaller number of spacers than the first region.

12. The IC structure of claim 11 , further comprising:
a first source/drain (S/D) contact in the first region, the first S/D contact between the two spacers on the second gate contact and the first gate contact.

13. The IC structure of claim 12 , the first region further comprising two spacers between the first gate contact and the first S/D contact.

14. The IC structure of claim 12 , further comprising a second S/D contact in the second region, and a single spacer between the second S/D contact and the second gate contact.

15. The IC structure of claim 14 , wherein a length of the first S/D contact is less than a length of the second S/D contact.

16. The IC structure of claim 11 , wherein at least one of the spacers has a thickness between 2 nanometers and 10 nanometers.

17. The IC structure of claim 11 , wherein a first distance from the first gate contact to the second gate contact is equal to a second distance from the second gate contact to the third gate contact.

18. The IC structure of claim 11 , wherein one of the two spacers in the first region is on a portion of a gate dielectric.

19. The IC structure of claim 18 , the second region comprising a single spacer on the second gate contact, wherein the single spacer is on a second portion of the gate dielectric.

20. The IC structure of claim 11 , wherein the second region comprises a single spacer that is in contact with the second gate contact and in contact with a source/drain contact in the second region.

Assignees

• Intel Corp

Inventors

• Bouche Guillaume
• Wei Andy Chih-Hung
• Ma Sean T

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D64/259

  Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric · CPC title

• H10D64/021 Primary

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title