Integrated circuit structures having maximized channel sizing

Patent metadata

Field	Value
Publication number	US-12471330-B2
Application number	US-202117547992-A
Country	US
Kind code	B2
Filing date	Dec 10, 2021
Priority date	Dec 10, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires having a first width; a second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires and having the first width; a first gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires;
a second gate structure portion over the second vertical stack of horizontal nanowires; and
a gate cut between the first gate structure portion and the second gate structure portion;
a third vertical stack of horizontal nanowires having a second width greater than the first width, the third vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the first vertical stack of horizontal nanowires; a fourth vertical stack of horizontal nanowires spaced apart from and parallel with the third vertical stack of horizontal nanowires and having the second width, the fourth vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the second vertical stack of horizontal nanowires; and a second gate structure continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

2 . The integrated circuit structure of claim 1 , further comprising a dielectric gate plug in the gate cut.

3 . The integrated circuit structure of claim 1 , wherein a first spacing between the third vertical stack of horizontal nanowires and the fourth vertical stack of horizontal nanowires is less than a second spacing between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires.

4 . The integrated circuit structure of claim 3 , wherein the first spacing is 10%-30% less than the second spacing.

5 . The integrated circuit structure of claim 1 , wherein the second width is 10%-30% greater than the first width.

6 . An integrated circuit structure, comprising:
a first fin having a first width; a second fin spaced apart from and parallel with the first fin and having the first width; a first gate structure, comprising:
a first gate structure portion over the first fin;
a second gate structure portion over the second fin; and
a gate cut between the first gate structure portion and the second gate structure portion;
a third fin having a second width greater than the first width, the third fin having a longest dimension along a same axis as a longest dimension of the first fin; a fourth fin spaced apart from and parallel with the third fin and having the second width, the fourth fin having a longest dimension along a same axis as a longest dimension of the second fin; and a second gate structure continuous over the third fin and over the fourth fin.

7 . The integrated circuit structure of claim 6 , further comprising a dielectric gate plug in the gate cut.

8 . The integrated circuit structure of claim 6 , wherein a first spacing between the third fin and the fourth fin is less than a second spacing between the first fin and the second fin.

9 . The integrated circuit structure of claim 8 , wherein the first spacing is 10%-30% less than the second spacing.

10 . The integrated circuit structure of claim 6 , wherein the second width is 10%-30% greater than the first width.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires having a first width;
a second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires and having the first width;
a first gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires;
a second gate structure portion over the second vertical stack of horizontal nanowires; and
a gate cut between the first gate structure portion and the second gate structure portion;

a third vertical stack of horizontal nanowires having a second width greater than the first width, the third vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the first vertical stack of horizontal nanowires;
a fourth vertical stack of horizontal nanowires spaced apart from and parallel with the third vertical stack of horizontal nanowires and having the second width, the fourth vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the second vertical stack of horizontal nanowires; and
a second gate structure continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a first fin having a first width;
a second fin spaced apart from and parallel with the first fin and having the first width;
a first gate structure, comprising:
a first gate structure portion over the first fin;
a second gate structure portion over the second fin; and
a gate cut between the first gate structure portion and the second gate structure portion;

a third fin having a second width greater than the first width, the third fin having a longest dimension along a same axis as a longest dimension of the first fin;
a fourth fin spaced apart from and parallel with the third fin and having the second width, the fourth fin having a longest dimension along a same axis as a longest dimension of the second fin; and
a second gate structure continuous over the third fin and over the fourth fin.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Yemenicioglu Sukru
• Ghani Tahir
• Wei Andy Chih-Hung
• Guler Leonard P
• Wallace Charles H
• Haran Mohit K

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title