Integrated circuit structures having maximized channel sizing

Patent metadata

Field	Value
Publication number	US-2026026057-A1
Application number	US-202519341431-A
Country	US
Kind code	A1
Filing date	Sep 26, 2025
Priority date	Dec 10, 2021
Publication date	Jan 22, 2026
Grant date	—

Abstract

A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

First claim

1 . (canceled)

2 . An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires having a first width along a first direction, the first vertical stack of horizontal nanowires having a source to drain direction along an axis along a second direction orthogonal to the first direction; and a second vertical stack of horizontal nanowires having a second width along the first direction, the second width different than the first width, the second vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

3 . The integrated circuit structure of claim 2 , further comprising:
a first gate structure over the first vertical stack of horizontal nanowires.

4 . The integrated circuit structure of claim 3 , further comprising:
a second gate structure over the second vertical stack of horizontal nanowires.

5 . The integrated circuit structure of claim 2 , further comprising:
a third vertical stack of horizontal nanowires having a third width along the first direction, the third width different than the first width and different than the second width, the third vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

6 . The integrated circuit structure of claim 2 , further comprising:
a third vertical stack of horizontal nanowires having a third width along the first direction, the third width the same as the first width, the third vertical stack of horizontal nanowires laterally spaced apart from the first vertical stack of horizontal nanowires along the first direction.

7 . A method of fabricating an integrated circuit structure, the method comprising:
forming a first vertical stack of horizontal nanowires having a first width along a first direction, the first vertical stack of horizontal nanowires having a source to drain direction along an axis along a second direction orthogonal to the first direction; and forming a second vertical stack of horizontal nanowires having a second width along the first direction, the second width different than the first width, the second vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

8 . The method of claim 7 , further comprising:
forming a first gate structure over the first vertical stack of horizontal nanowires.

9 . The method of claim 8 , further comprising:
forming a second gate structure over the second vertical stack of horizontal nanowires.

10 . The method of claim 7 , further comprising:
forming a third vertical stack of horizontal nanowires having a third width along the first direction, the third width different than the first width and different than the second width, the third vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

11 . The method of claim 7 , further comprising:
forming a third vertical stack of horizontal nanowires having a third width along the first direction, the third width the same as the first width, the third vertical stack of horizontal nanowires laterally spaced apart from the first vertical stack of horizontal nanowires along the first direction.

12 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires having a first width along a first direction, the first vertical stack of horizontal nanowires having a source to drain direction along an axis along a second direction orthogonal to the first direction; and
a second vertical stack of horizontal nanowires having a second width along the first direction, the second width different than the first width, the second vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

13 . The computing device of claim 12 , wherein the integrated circuit structure further comprises a third vertical stack of horizontal nanowires having a third width along the first direction, the third width different than the first width and different than the second width, the third vertical stack of horizontal nanowires having a source to drain direction along the axis along the second direction.

14 . The computing device of claim 12 , wherein the integrated circuit structure further comprises a third vertical stack of horizontal nanowires having a third width along the first direction, the third width the same as the first width, the third vertical stack of horizontal nanowires laterally spaced apart from the first vertical stack of horizontal nanowires along the first direction.

15 . The computing device of claim 12 , further comprising:
a memory coupled to the board.

16 . The computing device of claim 12 , further comprising:
a communication chip coupled to the board.

17 . The computing device of claim 12 , further comprising:
a battery coupled to the board.

18 . The computing device of claim 12 , further comprising:
a camera coupled to the board.

19 . The computing device of claim 12 , further comprising:
a display coupled to the board.

20 . The computing device of claim 12 , wherein the component is a packaged integrated circuit die.

21 . The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Yemenicioglu Sukru
• Ghani Tahir
• Wei Andy Chih-Hung
• Guler Leonard P
• Wallace Charles H
• Haran Mohit K

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title