Integrated circuit structure with buried power rail

Patent metadata

Field	Value
Publication number	US-2023207465-A1
Application number	US-202117561682-A
Country	US
Kind code	A1
Filing date	Dec 23, 2021
Priority date	Dec 23, 2021
Publication date	Jun 29, 2023
Grant date	—

Abstract

Integrated circuit structures having a buried power rail are described. In an example, an integrated circuit structure includes a device layer including a drain structure having an uppermost surface. A buried power rail is within the device layer and is neighboring the drain structure, the buried power rail having an uppermost surface below the uppermost surface of the drain structure. A top-side power rail is vertically over the buried power rail, the top-side power rail having a bottommost surface above the uppermost surface of the drain structure. A conductive structure is directly coupling the top-side power rail to the buried power rail.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a device layer comprising a drain structure having an uppermost surface; a buried power rail within the device layer and neighboring the drain structure, the buried power rail having an uppermost surface below the uppermost surface of the drain structure; a top-side power rail vertically over the buried power rail, the top-side power rail having a bottommost surface above the uppermost surface of the drain structure; and a conductive structure directly coupling the top-side power rail to the buried power rail.

2 . The integrated circuit structure of claim 1 , wherein a cell boundary of the device layer separates an active cell from a dummy cell, wherein the buried power rail is within both the active cell and the dummy cell, and wherein the drain structure is only within the active cell.

3 . The integrated circuit structure of claim 2 , wherein the conductive structure comprises a tall via structure, the tall via structure only within the dummy cell.

4 . The integrated circuit structure of claim 1 , wherein the conductive structure comprises one or more via structures, each via structure extending from the uppermost surface of the buried power rail to a location above the uppermost surface of the drain structure.

5 . The integrated circuit structure of claim 1 , wherein one or more trench contact layers are on the drain structure.

6 . The integrated circuit structure of claim 1 , wherein the buried power rail is vertically over and coupled to a bottom metallization structure, the bottom metallization structure exposed at a backside of the device layer.

7 . The integrated circuit structure of claim 1 , wherein the buried power rail is not coupled to the top-side power rail by a source structure.

8 . An integrated circuit structure, comprising:
an active cell separated from a dummy cell by a cell boundary; a buried power rail within both the active cell and the dummy cell; and a top-side power rail vertically over and coupled to the buried power rail, wherein the buried power rail is not coupled to the top-side power rail by a source structure.

9 . The integrated circuit structure of claim 8 , wherein the top-side power rail is coupled to the buried power rail by a tall via structure, the tall via structure only within the dummy cell.

10 . The integrated circuit structure of claim 8 , wherein the buried power rail is vertically over and coupled to a bottom metallization structure.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a device layer comprising a drain structure having an uppermost surface;
a buried power rail within the device layer and neighboring the drain structure, the buried power rail having an uppermost surface below the uppermost surface of the drain structure;
a top-side power rail vertically over the buried power rail, the top-side power rail having a bottommost surface above the uppermost surface of the drain structure; and
a conductive structure directly coupling the top-side power rail to the buried power rail.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:
a camera coupled to the board.

15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
an active cell separated from a dummy cell by a cell boundary;
a buried power rail within both the active cell and the dummy cell; and
a top-side power rail vertically over and coupled to the buried power rail, wherein the buried power rail is not coupled to the top-side power rail by a source structure.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , further comprising:
a camera coupled to the board.

20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Wei Andy Chih-Hung
• Park Changyok

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title