Stacked vias with bottom portions formed using selective growth

Patent metadata

Field	Value
Publication number	US-12211786-B2
Application number	US-202117197659-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Mar 10, 2021
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.

First claim

The invention claimed is:

1. An integrated circuit (IC) structure, comprising:
a first metallization layer and a second metallization layer, wherein the first metallization layer includes a first electrically conductive line, the second metallization layer includes a second electrically conductive line, and the second metallization layer is over the first metallization layer; and
a via having a first via portion coupled to the first electrically conductive line and a second via portion coupled to the second electrically conductive line,
wherein:
a dimension of the first via portion along a first axis of a plane that is parallel to the first metallization layer is substantially equal to a dimension of the first electrically conductive line along the first axis,
a dimension of the first via portion along a second axis of the plane that is parallel to the first metallization layer, the second axis being different from the first axis, is substantially equal to a dimension of the second electrically conductive line along the second axis,
a first face of the first via portion is substantially in a single plane with a first sidewall of the first electrically conductive line, and
a second face of the first via portion is substantially in a single plane with a second sidewall of the first electrically conductive line, wherein the second face of the first via portion is opposite the first face of the first via portion.

2. The IC structure according to claim 1 , wherein a dimension of the second via portion along the second axis is substantially equal to the dimension of the second electrically conductive line along the second axis.

3. The IC structure according to claim 1 , wherein:
a first face of the second via portion is substantially in a single plane with a first sidewall of the second electrically conductive line, and
a second face of the second via portion-is substantially in a single plane with a second sidewall of the second electrically conductive line, wherein the second face of the second via portion is opposite the first face of the second via portion.

4. The IC structure according to claim 1 , wherein:
a third face of the first via portion is substantially in a single plane with a first sidewall of the second electrically conductive line, and
a fourth face of the first via portion is substantially in a single plane with a second sidewall of the second electrically conductive line, wherein the fourth face of the first via portion is opposite the third face of the first via portion.

5. The IC structure according to claim 1 , wherein a distance between the first and second faces of the first via portion is smaller than a distance between two opposite faces of the second via portion.

6. The IC structure according to claim 1 , wherein the first face of the first via portion and the second face of the first via portion are substantially flat.

7. The IC structure according to claim 1 , wherein:
the first metallization layer includes a plurality of first electrically conductive lines,
the first electrically conductive line is one of the plurality of first electrically conductive lines, and
at least a portion of a top of another one of the plurality of first electrically conductive lines, different from the first electrically conductive line, has a capping material thereon.

8. An electronic device, comprising:
a circuit board;
an integrated circuit (IC) die, coupled to the circuit board;
a first metallization layer and a second metallization layer over the IC die, wherein the first metallization layer includes a bottom electrically conductive line, the second metallization layer includes a top electrically conductive line, and the first metallization layer is between the IC die and the second metallization layer; and
a via having a bottom via portion coupled to the bottom electrically conductive line and a top via portion coupled to the top electrically conductive line,
wherein:
the bottom via portion is self-aligned to the bottom electrically conductive line and the top via portion is self-aligned to the top electrically conductive line,
the first metallization layer includes a plurality of bottom electrically conductive lines,
the bottom electrically conductive line is a first bottom electrically conductive line of the plurality of bottom electrically conductive lines, and
at least a portion of a top of a second bottom electrically conductive line, different from the first bottom electrically conductive line, has a capping material thereon.

9. The electronic device according to claim 8 , wherein a portion of a top of the first bottom electrically conductive line that is not coupled to the bottom via portion has the capping material thereon.

10. The electronic device according to claim 9 , wherein a portion of the bottom via portion is in contact with the capping material.

11. The electronic device according to claim 9 , wherein the capping material is etch-selective with respect to a dielectric material enclosing sidewalls of the bottom electrically conductive line.

12. The electronic device according to claim 8 , further including one or more communication chips and an antenna.

13. The electronic device according to claim 8 , wherein the electronic device is a wearable electronic device or a handheld electronic device.

14. The electronic device according to claim 8 , wherein the electronic device is a motherboard.

15. An integrated circuit (IC) structure, comprising:
a first metallization layer and a second metallization layer, wherein the first metallization layer includes a first electrically conductive line, the second metallization layer includes a second electrically conductive line, and the second metallization layer is over the first metallization layer; and
a via having a first via portion coupled to the first electrically conductive line and a second via portion coupled to the second electrically conductive line,
wherein:
a dimension of the first via portion along a first axis of a plane that is parallel to the first metallization layer is substantially equal to a dimension of the first electrically conductive line along the first axis,
a dimension of the first via portion along a second axis of the plane that is parallel to the first metallization layer, the second axis being different from the first axis, is substantially equal to a dimension of the second electrically conductive line along the second axis,
a first face of the second via portion is substantially in a single plane with a first sidewall of the second electrically conductive line, and
a second face of the second via portion is substantially in a single plane with a second sidewall of the second electrically conductive line, wherein the second face of the second via portion is opposite the first face of the second via portion.

16. The IC structure according to claim 15 , wherein:
the first metallization layer includes a plurality of first electrically conductive lines,
the first electrically conductive line is one of the plurality of first electrically conductive lines, and
at least a portion of a top of another one of the plurality of first electrically conductive lines, different from the first electrically conductive line, has a capping material thereon.

17. The IC structure according to claim 15 , wherein:
a first face of the first via portion is substantially in a single plane with a first sidewall of the first electrically conductive line, and
a second face of the first via portion is substantially in a single plane with a second sidewall of the first

Assignees

• Intel Corp

Inventors

• Wei Andy Chih-Hung
• Bouche Guillaume

Classifications

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title