Integrated circuits with self-aligned tub architecture

Patent metadata

Field	Value
Publication number	US-2023207704-A1
Application number	US-202117561589-A
Country	US
Kind code	A1
Filing date	Dec 23, 2021
Priority date	Dec 23, 2021
Publication date	Jun 29, 2023
Grant date	—

Abstract

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
an n-channel metal oxide semiconductor (NMOS) transistor; a p-channel metal oxide semiconductor (PMOS) transistor; a bottom gate layer; a first gate wall coupled to the bottom gate layer; a second gate wall coupled to the bottom gate layer; and a third gate wall coupled to the bottom gate layer, wherein the NMOS transistor is disposed between the first gate wall and the second gate wall, the PMOS transistor is disposed between the second gate wall and the third gate wall, and the first, second, and third gate walls have a common height from the bottom gate layer.

2 . The integrated circuit structure of claim 1 , wherein NMOS transistor comprises a first plurality of silicon nano-ribbons and the PMOS transistor comprises a second plurality of silicon nano-ribbons.

3 . The integrated circuit structure of claim 2 , further comprising a gate spacer material between the first plurality of silicon nano-ribbons and: the first gate wall, the second gate wall, and the bottom gate layer.

4 . The integrated circuit structure of claim 2 , further comprising a gate spacer material between the second plurality of silicon nano-ribbons and: the second gate wall, the third gate wall, and the bottom gate layer.

5 . The integrated circuit structure of claim 1 , further comprising a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons.

6 . The integrated circuit structure of claim 5 , wherein the WFM layer or dipole layer is further coupled to at least a portion of the first gate wall and the second gate wall.

7 . The integrated circuit structure of claim 5 , wherein there is no WFM layer or dipole layer coupled to the second plurality of silicon nano-ribbons or the third gate wall.

8 . An integrated circuit structure, comprising:
a first n-channel metal oxide semiconductor (NMOS) transistor; a second NMOS transistor; a first p-channel metal oxide semiconductor (PMOS) transistor; a second PMOS transistor; a bottom gate layer; a first gate wall coupled to the bottom gate layer; a second gate wall coupled to the bottom gate layer; a third gate wall coupled to the bottom gate layer; a third gate wall coupled to the bottom gate layer; and a fifth gate wall coupled to the bottom gate layer, wherein the first NMOS transistor is disposed between the first gate wall and the second gate wall, the second NMOS transistor is disposed between the second gate wall and the third gate wall, the first PMOS transistor is disposed between the third gate wall and the fourth gate wall, the second PMOS transistor is disposed between the fourth gate wall and the fifth gate wall, and the first, second, third, fourth, and fifth gate walls have a common height from the bottom gate layer.

9 . The integrated circuit structure of claim 8 , wherein first NMOS transistor comprises a first plurality of silicon nano-ribbons and the second NMOS transistor comprises a second plurality of silicon nano-ribbons.

10 . The integrated circuit structure of claim 9 , further comprising a gate spacer material between the first plurality of silicon nano-ribbons and: the first gate wall, the second gate wall, and the bottom gate layer.

11 . The integrated circuit structure of claim 9 , further comprising a gate spacer material between the second plurality of silicon nano-ribbons and: the second gate wall, the third gate wall, and the bottom gate layer.

12 . The integrated circuit structure of claim 8 , further comprising a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons and the second plurality of silicon nano-ribbons.

13 . The integrated circuit structure of claim 12 , wherein the WFM layer or dipole layer is further coupled to at least a portion of: the first gate wall, second gate wall, third gate wall, and fourth gate wall.

14 . The integrated circuit structure of claim 13 , wherein the WFM layer or dipole layer is a first WFM layer or dipole layer, and wherein a second WFM layer or dipole layer is coupled to the first WFM layer or dipole layer.

15 . The integrated circuit structure of claim 14 , wherein the first PMOS transistor comprises a third plurality of silicon nano-ribbons and the second PMOS transistor comprises a fourth plurality of silicon nano-ribbons, wherein the first WFM layer or dipole layer is coupled to the third and fourth plurality of silicon nano-ribbons and at least a portion of the fourth and fifth gate walls, and the second WFM layer or dipole layer is coupled to the first WFM layer or dipole layer.

16 . The integrated circuit structure of claim 15 , wherein a third WFM layer or dipole layer is coupled to the second WFM layer or dipole layer that is coupled to the third and fourth plurality of silicon nano-ribbons and the at least a portion of the fourth and fifth gate walls.

17 . The integrated circuit structure of claim 16 , wherein a fourth WFM layer or dipole layer is coupled to the third WFM layer or dipole layer that is coupled to the third and fourth plurality of silicon nano-ribbons and the at least a portion of the fourth and fifth gate walls.

18 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
an n-channel metal oxide semiconductor (NMOS) transistor;
a p-channel metal oxide semiconductor (PMOS) transistor;
a bottom gate layer;
a first gate wall coupled to the bottom gate layer;
a second gate wall coupled to the bottom gate layer; and
a third gate wall coupled to the bottom gate layer, wherein the NMOS transistor is disposed between the first gate wall and the second gate wall, the PMOS transistor is disposed between the second gate wall and the third gate wall, and the first, second, and third gate walls have a common height from the bottom gate layer.

19 . The computing device of claim 18 , further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.

20 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a first n-channel metal oxide semiconductor (NMOS) transistor;
a second NMOS transistor;
a first p-channel metal oxide semiconductor (PMOS) transistor;
a second PMOS transistor;
a bottom gate layer;
a first gate wall coupled to the bottom gate layer;
a second gate wall coupled to the bottom gate layer;
a third gate wall coupled to the bottom gate layer;
a third gate wall coupled to the bottom gate layer; and
a fifth gate wall coupled to the bottom gate layer, wherein the first NMOS transistor is disposed between the first gate wall and the second gate wall, the second NMOS transistor is disposed between the second gate wall and the third gate wall, the first PMOS transistor is disposed between the third gate wall and the fourth gate wall, the second PMOS transistor is disposed between the fourth gate wall and the fifth gate wall, and the first, second, third, fourth, and fifth gate walls have a common height from the bottom gate layer.

21 . The computing device of claim 20 , further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.

Assignees

• Lavric Dan S
• Chiu Yenting
• Haran Mohit K
• Gardiner Allen B
• Guler Leonard P
• Wei Andy Chih Hung
• Ghani Tahir

Inventors

• Lavric Dan S
• Chiu Yenting
• Haran Mohit K
• Gardiner Allen B
• Guler Leonard P
• Wei Andy Chih-Hung
• Ghani Tahir

Classifications

• H10D30/801

  FETs having heterojunction gate electrodes · CPC title

• H10D30/721

  having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET  (TFTs having gate-to-body connection H10D30/6708) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title