Power rail between fins of a transistor structure

Patent metadata

Field	Value
Publication number	US-12506076-B2
Application number	US-202117359434-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a buried power rail (BPR) located within the transistor structure at a level below a height of one or more of the fins of the transistor structure. The BPR may be located proximate to a bottom substrate of the transistor structure. In embodiments, the transistor structure includes a protective layer, which can include one or more dielectric layers, above the BPR to protect the BPR during stages of transistor structure manufacture. In embodiments, portions of the protective layer may also be used to constrain epitaxial growth during stages of manufacturing of the transistor structure. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A transistor structure comprising:
a substrate having a bottommost surface; a plurality of fins that are substantially parallel with each other and substantially perpendicular to the substrate; a trench isolation structure laterally between adjacent ones of the plurality of fins, the trench isolation structure having a bottommost surface at a same level as a bottommost surface of the plurality of fins; and a power rail located between a first fin and a second fin of the plurality of fins and in a portion of the trench isolation structure, the power rail having a bottommost surface below a bottommost surface of the plurality of fins, the bottommost surface of the power rail at a same level as the bottommost surface of the substrate.

2 . The transistor structure of claim 1 , wherein the power rail is below a height of the plurality of fins.

3 . The transistor structure of claim 1 , wherein the plurality of fins include NMOS and PMOS fins.

4 . The transistor structure of claim 1 , wherein the power rail is surrounded by an oxide.

5 . The transistor structure of claim 1 , wherein the power rail is proximate to the substrate.

6 . The transistor structure of claim 1 , wherein the power rail is located between a barrier layer and the substrate, wherein the barrier layer protects the power rail during manufacture of the transistor structure.

7 . The transistor structure of claim 6 , wherein the barrier layer includes a dielectric.

8 . The transistor structure of claim 6 , further comprising an electrical contact electrically coupled to the power rail and extending through the barrier layer.

9 . The transistor structure of claim 8 , wherein the electrical contact is a through via structure or a through via bus structure.

10 . A transistor structure comprising:
a substrate having a bottommost surface; a plurality of fins that are substantially parallel with each other and substantially perpendicular to the substrate; a trench isolation structure laterally between adjacent ones of the plurality of fins, the trench isolation structure having a bottommost surface at a same level as a bottommost surface of the plurality of fins; a barrier layer above the substrate and substantially parallel to the substrate, wherein a portion of the barrier layer is substantially perpendicular to the substrate along sides of the plurality of fins wherein the barrier layer along the sides of the plurality of fins enclose part of an NMOS or PMOS epitaxy along a portion, respectively, of the plurality of fins; and a power rail below the barrier layer, the power rail located between a first fin and a second fin of the plurality of fins and in a portion of the trench isolation structure, the power rail having a bottommost surface below a bottommost surface of the plurality of fins, the bottommost surface of the power rail at a same level as the bottommost surface of the substrate.

11 . The transistor structure of claim 10 , further comprising a dielectric material coupled with a portion of barrier layer perpendicular to the substrate, wherein the dielectric material on an opposite side of the fin supports the portion of the barrier layer perpendicular to the substrate.

12 . The transistor structure of claim 11 , wherein the dielectric material on the opposite side of the fin supports the portion of the barrier layer perpendicular to the substrate during growth of the NMOS epitaxy or the PMOS epitaxy during transistor structure manufacture.

13 . The transistor structure of claim 10 , further comprising:
a contact etch stop layer (CESL) above the barrier layer and substantially parallel with the barrier layer.

14 . The transistor structure of claim 13 , wherein a portion of the CESL is not parallel with the barrier layer and extends along a side of the NMOS epitaxy or a side of the PMOS epitaxy.

15 . The transistor structure of claim 13 , further comprising an electrical contact extending from above the CESL, through the CESL and through the barrier layer toward the substrate.

16 . The transistor structure of claim 15 , wherein the electrical contact is electrically coupled with the power rail.

17 . A method for creating a transistor structure, the method comprising:
providing a substrate having a first side and a second side opposite the first side; forming a plurality of fins that are substantially parallel with each other and substantially perpendicular to the substrate on the first side of the substrate; forming a trench isolation structure laterally between adjacent ones of the plurality of fins, the trench isolation structure having a bottommost surface at a same level as a bottommost surface of the plurality of fins; and forming a power rail coupled with the first side of the substrate, the a power rail located between a first fin and a second fin of the plurality of fins and in a portion of the trench isolation structure, the power rail below a height of the plurality of fins, and the power rail having a bottommost surface below a bottommost surface of the plurality of fins, the bottommost surface of the power rail at a same level as the second side of the substrate.

18 . The method of claim 17 , further comprising:
encasing the power rail within an oxide; and applying a barrier layer on the oxide and above the power rail, the barrier layer protecting the power rail during subsequent manufacture of the transistor structure.

19 . The method of claim 18 , further comprising:
growing an NMOS epitaxy or a PMOS epitaxy on a top, respectively, of the plurality of fins; and depositing a contact etch stop layer (CESL) above the barrier layer, the CESL or the barrier layer at least partially surrounding the grown NMOS epitaxy or a PMOS epitaxy.

20 . The method of claim 19 , further comprising:
forming a conductive through via extending from above the CESL, through the CESL and through the barrier layer toward the substrate; and electrically coupling the conductive through via to the power rail.

Assignees

• Intel Corp

Inventors

• Wei Andy Chih-Hung
• Bouche Guillaume

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title